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86fa0255b2
The way the named arguments for various system instructions are handled at the
moment has a few problems:
- Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
- That weird Mapping class that I have no idea what I was on when I thought
it was a good idea.
- Searches are performed linearly through the entire list.
- We print absolutely all registers in upper-case, even though some are
canonically mixed case (SPSel for example).
- The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
to comments in our implementation, with a slightly opaque hex value
indicating the canonical encoding LLVM will use.
This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.
llvm-svn: 274576
49 lines
1.1 KiB
LLVM
49 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-none-eabi -mcpu=cortex-a57 2>&1 | FileCheck %s
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define i64 @read_encoded_register() nounwind {
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entry:
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; CHECK-LABEL: read_encoded_register:
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; CHECK: mrs x0, S1_2_C3_C4_5
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%reg = call i64 @llvm.read_register.i64(metadata !0)
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ret i64 %reg
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}
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define i64 @read_daif() nounwind {
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entry:
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; CHECK-LABEL: read_daif:
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; CHECK: mrs x0, DAIF
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%reg = call i64 @llvm.read_register.i64(metadata !1)
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ret i64 %reg
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}
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define void @write_encoded_register(i64 %x) nounwind {
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entry:
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; CHECK-LABEL: write_encoded_register:
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; CHECK: msr S1_2_C3_C4_5, x0
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call void @llvm.write_register.i64(metadata !0, i64 %x)
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ret void
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}
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define void @write_daif(i64 %x) nounwind {
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entry:
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; CHECK-LABEL: write_daif:
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; CHECK: msr DAIF, x0
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call void @llvm.write_register.i64(metadata !1, i64 %x)
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ret void
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}
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define void @write_daifset() nounwind {
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entry:
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; CHECK-LABEL: write_daifset:
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; CHECK: msr DAIFSet, #2
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call void @llvm.write_register.i64(metadata !2, i64 2)
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ret void
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}
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declare i64 @llvm.read_register.i64(metadata) nounwind
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declare void @llvm.write_register.i64(metadata, i64) nounwind
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!0 = !{!"1:2:3:4:5"}
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!1 = !{!"daif"}
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!2 = !{!"daifset"}
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