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3fdcf4e64c
If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs!
Motivating testcase:
void f(float *a, float *b, float *c, int n) {
while (n-- > 0)
*c++ = *a++ + *b++;
}
It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats register usage.
llvm-svn: 278658
60 lines
2.3 KiB
LLVM
60 lines
2.3 KiB
LLVM
; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; XFAIL: *
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;
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; Generate hardware loop when loop 'latch' block is different
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; from the loop 'exiting' block.
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; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
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; CHECK: endloop0
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define void @test(i32* nocapture %pFL, i16 signext %nBS, i16* nocapture readonly %pHT) #0 {
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entry:
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%0 = load i32, i32* %pFL, align 4
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%1 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %0, i32 246)
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%2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13)
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%3 = tail call i32 @llvm.hexagon.A2.sat(i64 %2)
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store i32 %3, i32* %pFL, align 4
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%cmp16 = icmp sgt i16 %nBS, 0
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br i1 %cmp16, label %for.body.lr.ph, label %for.end
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for.body.lr.ph:
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%4 = sext i16 %nBS to i32
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br label %for.body
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for.body:
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%5 = phi i32 [ %3, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
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%arrayidx3.phi = phi i32* [ %pFL, %for.body.lr.ph ], [ %arrayidx3.inc, %for.body.for.body_crit_edge ]
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%arrayidx5.phi = phi i16* [ %pHT, %for.body.lr.ph ], [ %arrayidx5.inc, %for.body.for.body_crit_edge ]
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%i.017.pmt = phi i32 [ 1, %for.body.lr.ph ], [ %phitmp, %for.body.for.body_crit_edge ]
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%6 = load i16, i16* %arrayidx5.phi, align 2
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%conv6 = sext i16 %6 to i32
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%7 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %5, i32 %conv6)
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%8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13)
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%9 = tail call i32 @llvm.hexagon.A2.sat(i64 %8)
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store i32 %9, i32* %arrayidx3.phi, align 4
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%exitcond = icmp eq i32 %i.017.pmt, %4
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%arrayidx3.inc = getelementptr i32, i32* %arrayidx3.phi, i32 1
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br i1 %exitcond, label %for.end.loopexit, label %for.body.for.body_crit_edge
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for.body.for.body_crit_edge:
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%arrayidx5.inc = getelementptr i16, i16* %arrayidx5.phi, i32 1
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%.pre = load i32, i32* %arrayidx3.inc, align 4
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%phitmp = add i32 %i.017.pmt, 1
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br label %for.body
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for.end.loopexit:
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br label %for.end
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for.end:
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ret void
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}
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declare i32 @llvm.hexagon.A2.sat(i64) #1
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declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
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declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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