Artyom Skrobov d49073b56a [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) ... llvm-svn: 194262		2013-11-08 16:17:14 +00:00
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AArch64	Implement AArch64 Neon instruction set Perm.	2013-11-06 03:35:27 +00:00
ARM	[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)	2013-11-08 16:17:14 +00:00
Mips	Support for microMIPS trap instructions 1.	2013-11-07 14:35:24 +00:00
SystemZ	[SystemZ] Add comparisons of high words and memory	2013-10-01 15:00:44 +00:00
X86	Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.	2013-10-14 01:42:32 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00