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https://github.com/RPCS3/llvm-mirror.git
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95cb757dac
This patch adds support for S_ANDN2, S_ORN2 32-bit and 64-bit instructions and adds splits to move them to the vector unit (for which there is no equivalent instruction). It modifies the way that the more complex scalar instructions are lowered to vector instructions by first breaking them down to sequences of simpler scalar instructions which are then lowered through the existing code paths. The pattern for S_XNOR has also been updated to apply inversion to one input rather than the output of the XOR as the result is equivalent and may allow leaving the NOT instruction on the scalar unit. A new tests for NAND, NOR, ANDN2 and ORN2 have been added, and existing tests now hit the new instructions (and have been modified accordingly). Differential: https://reviews.llvm.org/D54714 llvm-svn: 347877
104 lines
2.9 KiB
LLVM
104 lines
2.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
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; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
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; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
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; GCN-LABEL: {{^}}scalar_andn2_i32_one_use
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; GCN: s_andn2_b32
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define amdgpu_kernel void @scalar_andn2_i32_one_use(
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i32 addrspace(1)* %r0, i32 %a, i32 %b) {
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entry:
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%nb = xor i32 %b, -1
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%r0.val = and i32 %a, %nb
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_andn2_i64_one_use
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; GCN: s_andn2_b64
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define amdgpu_kernel void @scalar_andn2_i64_one_use(
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i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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entry:
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%nb = xor i64 %b, -1
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%r0.val = and i64 %a, %nb
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_orn2_i32_one_use
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; GCN: s_orn2_b32
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define amdgpu_kernel void @scalar_orn2_i32_one_use(
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i32 addrspace(1)* %r0, i32 %a, i32 %b) {
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entry:
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%nb = xor i32 %b, -1
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%r0.val = or i32 %a, %nb
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_orn2_i64_one_use
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; GCN: s_orn2_b64
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define amdgpu_kernel void @scalar_orn2_i64_one_use(
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i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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entry:
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%nb = xor i64 %b, -1
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%r0.val = or i64 %a, %nb
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_andn2_i32_s_v_one_use
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; GCN: v_not_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @vector_andn2_i32_s_v_one_use(
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i32 addrspace(1)* %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %v, -1
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%r0.val = and i32 %s, %not
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_andn2_i32_v_s_one_use
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; GCN: s_not_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @vector_andn2_i32_v_s_one_use(
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i32 addrspace(1)* %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %s, -1
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%r0.val = and i32 %v, %not
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_orn2_i32_s_v_one_use
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; GCN: v_not_b32
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; GCN: v_or_b32
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define amdgpu_kernel void @vector_orn2_i32_s_v_one_use(
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i32 addrspace(1)* %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %v, -1
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%r0.val = or i32 %s, %not
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_orn2_i32_v_s_one_use
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; GCN: s_not_b32
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; GCN: v_or_b32
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define amdgpu_kernel void @vector_orn2_i32_v_s_one_use(
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i32 addrspace(1)* %r0, i32 %s) {
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entry:
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%not = xor i32 %s, -1
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%r0.val = or i32 %v, %not
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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