..
GlobalISel
AMDGPU: Legalize more bitcasts
2019-01-20 19:45:18 +00:00
32-bit-local-address-space.ll
add3.ll
AMDGPU: Raise the priority of MAD24 in instruction selection.
2019-01-15 23:12:36 +00:00
add_i1.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
add_i64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
add_i128.ll
add_shl.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
add-debug.ll
add.i16.ll
add.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
add.v2i16.ll
AMDGPU: Make v2i16/v2f16 legal on VI
2018-05-22 06:32:10 +00:00
addrspacecast-captured.ll
AMDGPU: Fix using old address spaces in some tests
2018-12-05 17:34:59 +00:00
addrspacecast-constantexpr.ll
addrspacecast.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
adjust-writemask-invalid-copy.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
alignbit-pat.ll
alloca.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
always-uniform.ll
amdgcn.bitcast.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
amdgcn.private-memory.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
amdgpu-alias-analysis.ll
Allow subclassing ExternalAA
2018-11-07 20:26:42 +00:00
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll
[AMDGPU] Early expansion of 32 bit udiv/urem
2018-06-28 15:59:18 +00:00
amdgpu-codegenprepare-idiv.ll
[AMDGPU] Early expansion of 32 bit udiv/urem
2018-06-28 15:59:18 +00:00
amdgpu-inline.ll
amdgpu-shader-calling-convention.ll
amdgpu.private-memory.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
amdpal_scratch_mergedshader.ll
[AMDGPU] Enable LICM in the BE pipeline
2018-06-29 16:26:53 +00:00
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
2018-04-10 11:25:15 +00:00
and_or.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
and-gcn.ll
and.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
andorbitset.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
andorn2.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
andorxorinvimm.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
annotate-kernel-features-hsa-call.ll
Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute
2018-12-13 21:23:12 +00:00
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
atomic_cmp_swap_local.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
atomic_load_add.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_load_local.ll
AMDGPU: Add patterns for i32/i64 local atomic load/store
2018-06-22 08:39:52 +00:00
atomic_load_sub.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_global_pointer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Fix the new atomic optimizer in pixel shaders.
2018-11-05 12:04:48 +00:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_store_local.ll
AMDGPU: Add patterns for i32/i64 local atomic load/store
2018-06-22 08:39:52 +00:00
atomicrmw-nand.ll
AMDGPU: Expand atomicrmw nand in IR
2018-10-02 03:50:56 +00:00
attr-amdgpu-flat-work-group-size-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
attr-amdgpu-flat-work-group-size.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
attr-amdgpu-num-sgpr-spill-to-smem.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
attr-amdgpu-num-sgpr.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
basic-call-return.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
bfi_int.ll
AMDGPU: Scalarize vector argument types to calls
2018-07-31 19:05:14 +00:00
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll
AMDGPU: Fix assertion with bitcast from i64 constant to v4i16
2018-11-02 02:43:55 +00:00
bitcast-v4f16-v4i16.ll
AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts
2018-12-19 22:53:33 +00:00
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
AMDGPU: Use scavengeRegisterBackwards
2018-10-30 01:33:14 +00:00
branch-relaxation.ll
[MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM
2018-12-05 03:41:26 +00:00
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll
buffer-schedule.ll
bug-vopc-commute.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
build_vector.ll
build-vector-insert-elt-infloop.ll
[LICM] Use ICFLoopSafetyInfo in LICM
2018-11-06 02:44:49 +00:00
build-vector-packed-partial-undef.ll
AMDGPU: Fix packing undef parts of build_vector
2018-08-12 08:42:46 +00:00
byval-frame-setup.ll
AMDGPU: Cleanup / relax tests for future changes
2018-11-26 17:17:07 +00:00
call_fs.ll
call-argument-types.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
call-constexpr.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
call-encoding.ll
call-graph-register-usage.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
call-preserved-registers.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
call-return-types.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
callee-frame-setup.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
callee-special-input-sgprs.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
callee-special-input-vgprs.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
calling-conventions.ll
AMDGPU: Partially fix handling of packed amdgpu_ps arguments
2018-08-01 19:57:34 +00:00
captured-frame-index.ll
cayman-loop-bug.ll
cf_end.ll
cf-loop-on-constant.ll
AMDGPU: Try a lot harder to emit scalar loads
2018-06-07 09:54:49 +00:00
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
cgp-bitfield-extract.ll
[DAGCombiner] re-enable truncation of binops
2018-12-08 16:07:38 +00:00
chain-hi-to-lo.ll
AMDGPU: Adjust the chain for loads writing to the HI part of a register.
2019-01-16 21:32:53 +00:00
clamp-modifier.ll
AMDGPU: Improve hack for packing conversion ops
2018-08-01 20:13:58 +00:00
clamp-omod-special-case.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
clamp.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cndmask-no-def-vcc.ll
[DAG] add undef simplifications for select nodes
2018-11-18 17:36:23 +00:00
coalescer_distribute.ll
AMDGPU: Don't use spir_kernel in a test
2018-07-05 17:01:29 +00:00
coalescer_remat.ll
coalescer-extend-pruned-subrange.mir
Improve handling of COPY instructions with identical value numbers
2018-06-25 13:46:41 +00:00
coalescer-identical-values-undef.mir
Improve handling of COPY instructions with identical value numbers
2018-06-25 13:46:41 +00:00
coalescer-subranges-another-copymi-not-live.mir
Improve handling of COPY instructions with identical value numbers
2018-06-25 13:46:41 +00:00
coalescer-subranges-another-prune-error.mir
AMDGPU: Improve hack for packing conversion ops
2018-08-01 20:13:58 +00:00
coalescer-subreg-join.mir
AMDGPU: Turn D16 for MIMG instructions into a regular operand
2018-06-21 13:36:01 +00:00
coalescer-subregjoin-fullcopy.mir
Improve handling of COPY instructions with identical value numbers
2018-06-25 13:46:41 +00:00
coalescer-with-subregs-bad-identical.mir
Improve handling of COPY instructions with identical value numbers
2018-06-25 13:46:41 +00:00
coalescing-with-subregs-in-loop-bug.mir
Improve handling of COPY instructions with identical value numbers
2018-06-25 13:46:41 +00:00
code-object-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf.ll
[AMDGPU] Enable LICM in the BE pipeline
2018-06-29 16:26:53 +00:00
combine_vloads.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
combine-and-sext-bool.ll
combine-cond-add-sub.ll
[AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299".
2018-05-02 18:16:39 +00:00
combine-ftrunc.ll
comdat.ll
[AMDGPU] Fix compilation failure when IR contains comdat
2018-05-11 20:40:14 +00:00
commute_modifiers.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
commute-compares.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
commute-shifts.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll
[SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR
2018-12-07 09:18:44 +00:00
concat_vectors.ll
DAG: Fix creating concat_vectors with illegal type
2018-06-15 12:09:15 +00:00
constant-address-space-32bit.ll
AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes
2018-08-29 20:03:00 +00:00
constant-fold-imm-immreg.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
constant-fold-mi-operands.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
control-flow-fastregalloc.ll
RegAllocFast: Leave unassigned virtreg entries in map
2018-11-07 06:57:03 +00:00
control-flow-optnone.ll
convergent-inlineasm.ll
copy-illegal-type.ll
[DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.
2018-08-28 03:47:20 +00:00
copy-to-reg.ll
couldnt-join-subrange-3.mir
AMDGPU: Improve hack for packing conversion ops
2018-08-01 20:13:58 +00:00
cross-block-use-is-not-abi-copy.ll
DAG: Don't use ABI copies in some contexts
2018-08-30 05:49:28 +00:00
ctlz_zero_undef.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
ctlz.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
ctpop16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
ctpop64.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
ctpop.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll
[AMDGPU] Fix dwordx3/southern-islands failures.
2019-01-10 16:21:08 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll
AMDGPU: Fix DAG divergence not reporting flat loads
2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll
[AMDGPU] Early expansion of 32 bit udiv/urem
2018-06-28 15:59:18 +00:00
dagcombine-setcc-select.ll
[AMDGPU] Disable DAG combine at -O0
2018-11-27 15:13:37 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dead_copy.mir
debug-value2.ll
Remove irrelevant references to legacy git repositories from
2019-01-15 16:18:52 +00:00
debug-value.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
debug.ll
debugger-emit-prologue.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
debugger-insert-nops.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
default-fp-mode.ll
AMDGPU: Remove llvm.AMDGPU.kill
2018-12-07 17:46:16 +00:00
detect-dead-lanes.mir
directive-amdgcn-target.ll
AMDGPU: Add sram-ecc feature
2018-11-05 22:44:19 +00:00
disconnected-predset-break-bug.ll
div_i128.ll
AMDGPU: Error more gracefully on libcalls
2018-08-08 16:58:39 +00:00
diverge-extra-formal-args.ll
[AMDGPU] Fix issues for backend divergence tracking
2018-04-18 13:53:31 +00:00
diverge-interp-mov-lower.ll
[AMDGPU] Fix issues for backend divergence tracking
2018-04-18 13:53:31 +00:00
diverge-switch-default.ll
[AMDGPU] restore r342722 which was reverted with r342743
2018-09-25 09:39:21 +00:00
divergent-branch-uniform-condition.ll
AMDGPU: test for uniformity of branch instruction, not its condition
2019-01-07 15:52:28 +00:00
divrem24-assume.ll
[AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion
2018-07-25 17:02:11 +00:00
dpp_combine_subregs.mir
Revert "[AMDGPU] Fix DPP combiner"
2019-01-09 15:21:53 +00:00
dpp_combine.ll
Revert "[AMDGPU] Fix DPP combiner"
2019-01-09 15:21:53 +00:00
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2.ll
ds_read2st64.ll
ds_write2.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
ds_write2st64.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
ds-combine-large-stride.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
dynamic_stackalloc.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll
[AMDGPU] Fix dwordx3/southern-islands failures.
2019-01-10 16:21:08 +00:00
early-if-convert.ll
early-inline-alias.ll
early-inline.ll
Reapply "AMDGPU: Force inlining if LDS global address is used"
2018-07-10 14:03:41 +00:00
elf-header-flags-mach.ll
AMDGPU: Add sram-ecc feature
2018-11-05 22:44:19 +00:00
elf-header-flags-sram-ecc.ll
AMDGPU: Add sram-ecc feature
2018-11-05 22:44:19 +00:00
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
elf.ll
elf.metadata.ll
[AMDGPU] Change section name with metadata access
2019-01-03 11:22:58 +00:00
elf.r600.ll
else.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
AMDGPU: Don't delete instructions if S_ENDPGM has implicit uses
2018-08-28 18:55:55 +00:00
enqueue-kernel.ll
[AMDGPU] Change enqueue kernel handle type
2018-06-13 17:31:51 +00:00
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extload-private.ll
extload.ll
extract_vector_dynelt.ll
[AMDGPU] combine extractelement into several selects
2018-11-13 21:18:21 +00:00
extract_vector_elt-f16.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll
[AMDGPU] combine extractelement into several selects
2018-11-13 21:18:21 +00:00
extract_vector_elt-i8.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
extract_vector_elt-i16.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract_vector_elt-i64.ll
[AMDGPU] combine extractelement into several selects
2018-11-13 21:18:21 +00:00
extract-lowbits.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
extract-subvector-equal-length.ll
[CodeGen] Fix assert in SelectionDAG::computeKnownBits
2018-08-13 18:44:21 +00:00
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
fabs.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fabs.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
fadd64.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fadd.ll
Utilize new SDNode flag functionality to expand current support for fadd
2018-06-18 23:44:59 +00:00
fcanonicalize-elimination.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fcanonicalize.f16.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
fcanonicalize.ll
AMDGPU: Expand vector canonicalizes
2018-09-18 01:51:33 +00:00
fceil64.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
fcmp.ll
fconst64.ll
fcopysign.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fcopysign.f32.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fcopysign.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fdiv32-to-rcp-folding.ll
[AMDGPU] Fix scalar operand folding bug that causes SHOC performance regression.
2019-01-03 19:55:32 +00:00
fdiv.f16.ll
Utilize new SDNode flag functionality to expand current support for fdiv
2018-06-15 20:44:55 +00:00
fdiv.f64.ll
fdiv.ll
fdot2.ll
AMDGPU: Fix V_FMA_F16 selection on GFX9
2018-11-19 21:10:16 +00:00
fence-barrier.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
ffloor.f64.ll
ffloor.ll
fix-vgpr-copies.mir
fix-wwm-liveness.mir
[AMDGPU] Reworked SIFixWWMLiveness
2018-08-02 23:31:32 +00:00
flat_atomics_i64.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
flat_atomics.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
flat-address-space.ll
flat-for-global-subtarget-feature.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
flat-load-clustering.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
flat-scratch-reg.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fmad.ll
fmax3.f64.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax3.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax_legacy.f64.ll
AMDGPU: Cleanup min/max legacy tests
2018-08-12 19:29:53 +00:00
fmax_legacy.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmaxnum.r600.ll
AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests
2018-07-31 20:38:42 +00:00
fmed3.ll
AMDGPU: Don't form fmed3 if it will require materialization
2018-09-18 02:34:54 +00:00
fmin3.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin_fmax_legacy.amdgcn.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin_legacy.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin_legacy.f64.ll
AMDGPU: Cleanup min/max legacy tests
2018-08-12 19:29:53 +00:00
fmin_legacy.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin.ll
fminnum.f64.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fminnum.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fminnum.r600.ll
AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests
2018-07-31 20:38:42 +00:00
fmul64.ll
fmul-2-combine-multi-use.ll
DAG: Enhance isKnownNeverNaN
2018-08-03 18:27:52 +00:00
fmul.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fmul.ll
fmuladd.f16.ll
fmuladd.f32.ll
AMDGPU: Add Vega12 and Vega20
2018-04-30 19:08:16 +00:00
fmuladd.f64.ll
fmuladd.v2f16.ll
[AMDGPU] Enabled v2.16 literals for VOP3P
2018-04-17 23:09:05 +00:00
fnearbyint.ll
fneg-combines.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fneg-combines.si.ll
AMDGPU: Address todo for handling 1/(2 pi)
2018-08-15 21:03:55 +00:00
fneg-fabs.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fneg-fabs.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fneg-fabs.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
fneg.f16.ll
AMDGPU: Use scalar operations for f16 fabs/fneg patterns
2018-06-07 10:15:20 +00:00
fneg.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fneg.ll
fold-cndmask.mir
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir
[AMDGPU] Preliminary patch for divergence driven instruction selection. Operands Folding 1.
2018-08-30 13:55:04 +00:00
fold-imm-f16-f32.mir
fold-immediate-operand-shrink-with-carry.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
fold-immediate-operand-shrink.mir
Don't count debug instructions towards neighborhood count
2018-08-30 07:18:19 +00:00
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fold-vgpr-copy.mir
[AMDGPU] Fold copy (copy vgpr)
2018-09-27 18:55:20 +00:00
force-alwaysinline-lds-global-address-codegen.ll
AMDGPU: Always run AMDGPUAlwaysInline
2018-10-03 02:47:25 +00:00
force-alwaysinline-lds-global-address.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
fp_to_uint.f64.ll
fp_to_uint.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
fp-classify.ll
AMDGPU: Combine and of seto/setuo and fp_class
2018-08-10 18:58:56 +00:00
fpext-free.ll
AMDGPU: Fix V_FMA_F16 selection on GFX9
2018-11-19 21:10:16 +00:00
fpext.f16.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub64.ll
fsub.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fsub.ll
ftrunc.f64.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
ftrunc.ll
function-args.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
function-returns.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
gep-address-space.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
gfx902-without-xnack.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
global_atomics_i64.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
global_atomics.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
global_smrd_cfg.ll
global_smrd.ll
AMDGPU: Use GOT PSV since it has an address space now
2018-09-10 02:23:39 +00:00
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-load-store-atomics.mir
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
global-saddr.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
global-smrd-unknown.ll
AMDGPU: Don't use undef in a test
2018-05-08 18:43:34 +00:00
global-variable-relocs.ll
gv-const-addrspace.ll
gv-offset-folding.ll
half.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
hazard-buffer-store-v-interp.mir
[AMDGPU] Add VALU to V_INTERP Instructions
2018-07-05 12:02:07 +00:00
hazard-inlineasm.mir
hazard.mir
[AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting
2018-09-10 10:14:48 +00:00
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-func-align.ll
hsa-func.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-globals.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueu-kernel-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-enqueue-kernel.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-metadata-from-llvm-ir-full-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-from-llvm-ir-full.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-metadata-hidden-args-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-hidden-args.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-metadata-images-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-images.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-metadata-invalid-ocl-version-1-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props-v3.ll
[AMDGPU] Emit MessagePack HSA Metadata for v3 code object
2018-12-12 19:39:27 +00:00
hsa-metadata-kernel-code-props.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-metadata-kernel-debug-props.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa-note-no-func.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
hsa.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
huge-private-buffer.ll
i1-copy-from-loop.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
i1-copy-phi.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll
[AMDGPU] Enable LICM in the BE pipeline
2018-06-29 16:26:53 +00:00
idot2.ll
AMDGPU: Actually commit re-run of update_llc_test_checks
2018-08-31 15:05:06 +00:00
idot4.ll
[AMDGPU] Match signed dot4/8 pattern.
2018-10-04 16:57:37 +00:00
idot8.ll
[SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts simplification
2018-12-01 12:08:55 +00:00
illegal-sgpr-to-vgpr-copy.ll
image-attributes.ll
image-resource-id.ll
image-schedule.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
imm16.ll
[DAGCombiner] allow narrowing of add followed by truncate
2018-12-22 17:10:31 +00:00
imm.ll
[AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands
2019-01-18 15:17:17 +00:00
immv216.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
indirect-addressing-si-gfx9.ll
AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing.
2018-12-21 20:57:34 +00:00
indirect-addressing-si-noopt.ll
[AMDGPU] Disable DAG combine at -O0
2018-11-27 15:13:37 +00:00
indirect-addressing-si-pregfx9.ll
AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing.
2018-12-21 20:57:34 +00:00
indirect-addressing-si.ll
AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing.
2018-12-21 20:57:34 +00:00
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll
[MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM
2018-12-05 03:41:26 +00:00
inline-asm.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
inline-attr.ll
inline-calls.ll
inline-constraints.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-16.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-illegal-type.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_dynelt.ll
[AMDGPU] Convert insert_vector_elt into set of selects
2018-11-19 17:39:20 +00:00
insert_vector_elt.ll
[AMDGPU] Extend the SI Load/Store optimizer to combine more things.
2018-12-12 16:15:21 +00:00
insert_vector_elt.v2i16.ll
[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST
2018-11-16 01:13:34 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST
2018-11-16 01:13:34 +00:00
insert_vector_elt.v2i16.subtest-saddr.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
insert-skip-from-vcc.mir
[AMDGPU] Optimize S_CBRANCH_VCC[N]Z -> S_CBRANCH_EXEC[N]Z
2018-11-12 18:48:17 +00:00
insert-skips-kill-uncond.mir
AMDGPU: Add implicit def of SCC to kill and indirect pseudos
2018-06-21 13:36:08 +00:00
insert-waitcnts-callee.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
insert-waitcnts-exp.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
inserted-wait-states.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
internalize.ll
AMDGPU: Stop forcing internalize at -O0
2018-08-31 06:02:36 +00:00
invalid-addrspacecast.ll
AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit
2018-09-10 11:59:27 +00:00
invalid-alloca.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
ipra.ll
jump-address.ll
[AMDGPU] change test to avoid NaN math
2018-03-19 19:26:22 +00:00
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll
AMDGPU: Fix offsets for < 4-byte aggregate kernel arguments
2018-12-07 22:12:17 +00:00
kernel-argument-dag-lowering.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
known-never-nan.ll
DAG: Handle extract_vector_elt in isKnownNeverNaN
2018-09-03 14:01:03 +00:00
known-never-snan.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
knownbits-recursion.ll
large-alloca-compute.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
large-alloca-graphics.ll
large-constant-initializer.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll
lds_atomic_f32.ll
lds-alignment.ll
lds-bounds.ll
AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI
2018-10-17 15:37:48 +00:00
lds-global-non-entry-func.ll
AMDGPU: Error on LDS global address in functions
2018-06-08 08:05:54 +00:00
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
lds-zero-initializer.ll
legalize-fp-load-invariant.ll
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.buffer.atomic.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
[AMDGPU] Fix dwordx3/southern-islands failures.
2019-01-10 16:21:08 +00:00
llvm.amdgcn.buffer.store.format.d16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.buffer.store.format.ll
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
2018-04-26 16:11:19 +00:00
llvm.amdgcn.buffer.store.ll
[AMDGPU] Extend the SI Load/Store optimizer to combine more things.
2018-12-12 16:15:21 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
llvm.amdgcn.div.fixup.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.ordered.add.ll
AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
2019-01-16 15:43:53 +00:00
llvm.amdgcn.ds.ordered.swap.ll
AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
2019-01-16 15:43:53 +00:00
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
AMDGPU: Force skip over s_sendmsg and exp instructions
2018-07-30 09:23:59 +00:00
llvm.amdgcn.fcmp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmad.ftz.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
AMDGPU: Add a fast path for icmp.i1(src, false, NE)
2019-01-15 02:13:18 +00:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.atomic.dim.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.dim.ll
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Add support for a16 modifiear for gfx9
2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
AMDGPU: Dimension-aware image intrinsics
2018-04-04 10:58:54 +00:00
llvm.amdgcn.image.gather4.dim.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.gather4.o.dim.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.getlod.dim.ll
AMDGPU: Select MIMG instructions manually in SITargetLowering
2018-06-21 13:36:57 +00:00
llvm.amdgcn.image.load.a16.d16.ll
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.load.a16.ll
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Add support for a16 modifiear for gfx9
2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
2019-01-14 11:55:24 +00:00
llvm.amdgcn.image.sample.ltolz.ll
[AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero
2018-08-01 12:12:01 +00:00
llvm.amdgcn.image.sample.o.dim.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
[AMDGPU] Avoid using divergent value in mubuf addr64 descriptor
2018-08-02 22:53:57 +00:00
llvm.amdgcn.init.exec.ll
AMDGPU: Fix a corner case crash in SIOptimizeExecMasking
2018-04-23 13:05:50 +00:00
llvm.amdgcn.interp.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
llvm.amdgcn.kill.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
llvm.amdgcn.mov.dpp.ll
run post-RA hazard recognizer pass late
2018-07-16 10:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.ps.live.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
llvm.amdgcn.raw.buffer.atomic.ll
AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics
2018-10-08 16:53:48 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Handle OR as operand of raw load/store
2019-01-02 09:47:41 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Handle OR as operand of raw load/store
2019-01-02 09:47:41 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Extend the SI Load/Store optimizer to combine more things.
2018-12-12 16:15:21 +00:00
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
llvm.amdgcn.sad.hi.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.sdot4.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.sdot8.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.sendmsg.ll
AMDGPU: Force skip over s_sendmsg and exp instructions
2018-07-30 09:23:59 +00:00
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.struct.buffer.atomic.ll
AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics
2018-10-08 16:53:48 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics
2018-10-03 10:29:43 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Allow int types for MUBUF vdata
2018-08-21 11:08:12 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.tbuffer.store.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.udot4.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.udot8.ll
AMDGPU: Add clamp bit to dot intrinsics
2018-08-01 01:31:30 +00:00
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
[AMDGPU]: Turn on the DPP combiner by default
2018-12-05 15:21:17 +00:00
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.workgroup.id.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
llvm.amdgcn.workitem.id.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
llvm.amdgcn.wqm.vote.ll
AMDGPU: Remove llvm.AMDGPU.kill
2018-12-07 17:46:16 +00:00
llvm.amdgcn.writelane.ll
AMDGPU: Fix getInstSizeInBytes
2018-08-29 07:46:09 +00:00
llvm.ceil.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll
[AMDGPU] Ensure trig range reduction only used for subtargets that require it
2018-09-14 10:27:19 +00:00
llvm.cos.ll
llvm.dbg.value.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.exp2.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.exp2.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
llvm.floor.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.fmuladd.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log2.f16.ll
llvm.log2.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
llvm.log10.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log10.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.maxnum.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
llvm.memcpy.ll
llvm.minnum.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll
[AMDGPU] Ensure trig range reduction only used for subtargets that require it
2018-09-14 10:27:19 +00:00
llvm.sin.ll
[AMDGPU] Ensure trig range reduction only used for subtargets that require it
2018-09-14 10:27:19 +00:00
llvm.sqrt.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.trunc.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
load-constant-f32.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-f64.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-constant-i8.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
load-constant-i16.ll
AMDGPU: Fix selection error on constant loads with < 4 byte alignment
2018-03-29 19:59:28 +00:00
load-constant-i32.ll
[AMDGPU] Split v32i32 loads
2018-08-31 22:43:36 +00:00
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-global-i8.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
load-global-i16.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
load-global-i32.ll
[AMDGPU] Split v32i32 loads
2018-08-31 22:43:36 +00:00
load-global-i64.ll
load-hi16.ll
AMDGPU: Add D16 instructions preserve unused bits feature
2018-05-04 20:06:57 +00:00
load-input-fold.ll
load-lo16.ll
Implement computeKnownBits for scalar_to_vector
2018-11-19 23:34:07 +00:00
load-local-f32-no-ds128.ll
AMDGPU: Add a missing test for the 128-bit local addr space option
2018-05-15 21:41:57 +00:00
load-local-f32.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-f64.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-local-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-local-i8.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-local-i16.ll
[SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes
2018-10-30 10:32:11 +00:00
load-local-i32.ll
[AMDGPU] Split v32i32 loads
2018-08-31 22:43:36 +00:00
load-local-i64.ll
AMDGPU: enable 128-bit for local addr space under an option
2018-04-10 22:48:23 +00:00
load-select-ptr.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
load-weird-sizes.ll
local-64.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
local-atomics64.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
local-atomics.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
loop_break.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
loop_exit_with_xor.ll
[AMDGPU] Fixed incorrect break from loop
2018-05-25 07:55:04 +00:00
loop-address.ll
loop-idiom.ll
lower-kernargs.ll
AMDGPU: Stop trying to extend arguments for clover
2018-07-28 12:34:25 +00:00
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
[TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24.
2019-01-07 19:30:43 +00:00
lshr.v2i16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
mad_int24.ll
mad_uint24.ll
AMDGPU: Remove broken i16 ternary patterns
2018-08-07 21:54:37 +00:00
mad-combine.ll
mad-mix-hi.ll
AMDGPU: Remove custom BUILD_VECTOR combine
2018-10-30 01:37:59 +00:00
mad-mix-lo.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
mad-mix.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
madak-inline-constant.mir
[AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32.
2018-09-10 16:42:49 +00:00
madak.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
madmk.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
max3.ll
max-literals.ll
max.i16.ll
max.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
mem-builtins.ll
memory_clause.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
memory_clause.mir
AMDGPU: Turn D16 for MIMG instructions into a regular operand
2018-06-21 13:36:01 +00:00
memory-legalizer-amdpal.ll
[AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.
2018-12-10 16:35:53 +00:00
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-insert-end.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-addrspace.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-load.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
memory-legalizer-local.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-mesa3d.ll
[AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.
2018-12-10 16:35:53 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
memory-legalizer-region.mir
[AMDGPU] Simplify memory legalizer
2018-06-07 22:28:32 +00:00
memory-legalizer-store-infinite-loop.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
memory-legalizer-store.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
merge-load-store-physreg.mir
merge-load-store-vreg.mir
[AMDGPU] Fix ds combine with subregs
2018-09-25 23:33:18 +00:00
merge-load-store.mir
merge-m0.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
[AMDGPU] Fix dwordx3/southern-islands failures.
2019-01-10 16:21:08 +00:00
mesa_regression.ll
min3.ll
min.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
misched-killflags.mir
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
missing-store.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
mode-register.mir
[AMDGPU] Add new Mode Register pass
2018-12-10 12:06:10 +00:00
move-addr64-rsrc-dead-subreg-writes.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
[AMDGPU] Convert insert_vector_elt into set of selects
2018-11-19 17:39:20 +00:00
movrels-bug.mir
mubuf-legalize-operands.ll
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions
2018-10-08 18:47:01 +00:00
mubuf-legalize-operands.mir
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions
2018-10-08 18:47:01 +00:00
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
AMDGPU: Remove llvm.SI.buffer.load.dword
2018-12-07 17:46:20 +00:00
mul_int24.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
mul_uint24-amdgcn.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
mul_uint24-r600.ll
mul.i16.ll
AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls
2018-07-31 19:17:47 +00:00
mul.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
multi-divergent-exit-region.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
multilevel-break.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
nand.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
nested-calls.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
nested-loop-conditions.ll
AMDGPU: Remove PHI loop condition optimization
2018-10-31 13:26:48 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-shrink-extloads.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
noop-shader-O0.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
nop-data.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
nor.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
not-scalarize-volatile-load.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
nullptr.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
omod-nsz-flag.mir
AMDGPU: Check NSZ MI flag when folding omod
2018-08-12 08:44:25 +00:00
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
opt-sgpr-to-vgpr-copy.mir
optimize-if-exec-masking.mir
Fix MachineInstr::findRegisterUseOperandIdx subreg checks
2018-11-12 18:12:28 +00:00
optimize-negated-cond-exec-masking.mir
[AMDGPU] Simplify negated condition
2018-12-13 03:17:40 +00:00
optimize-negated-cond.ll
[AMDGPU] Simplify negated condition
2018-12-13 03:17:40 +00:00
or3.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
or.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
over-max-lds-size.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
RegAllocFast: Leave unassigned virtreg entries in map
2018-11-07 06:57:03 +00:00
partial-shift-shrink.ll
AMDGPU: Handle partial shift reduction for variable shifts
2018-05-09 20:52:54 +00:00
partially-dead-super-register-immediate.ll
perfhint.ll
[AMDGPU] Do not consider indirect acces through phi for wave limiter
2018-06-11 16:50:49 +00:00
permute.ll
[AMDGPU] Corrected computeKnownBits for V_PERM_B32
2018-06-13 18:52:54 +00:00
phi-elimination-assertion.mir
[PHIElimination] Lower a PHI node with only undef uses as IMPLICIT_DEF
2018-09-30 17:26:58 +00:00
pk_max_f16_literal.ll
[AMDGPU] Truncate packed inline constant
2018-04-24 18:17:55 +00:00
postra-norename.mir
predicate-dp4.ll
predicates.ll
print-mir-custom-pseudo.ll
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
2018-10-03 03:38:22 +00:00
private-access-no-objects.ll
private-element-size.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll
AMDGPU: Increase default stack alignment
2018-03-29 20:22:04 +00:00
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
promote-alloca-padding-size-estimate.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
AMDGPU: Add an option -disable-promote-alloca-to-lds
2018-11-06 21:28:17 +00:00
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
AMDGPU: Fix using old address spaces in some tests
2018-12-05 17:34:59 +00:00
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
[AMDGPU] Convert insert_vector_elt into set of selects
2018-11-19 17:39:20 +00:00
promote-alloca-volatile.ll
promote-constOffset-to-imm.ll
[AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions.
2018-12-14 21:13:14 +00:00
promote-constOffset-to-imm.mir
[AMDGPU] Removed the unnecessary operand size-check-assert from processBaseWithConstOffset().
2018-12-18 19:58:39 +00:00
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
AMDGPU: Fix r600 test
2018-09-11 04:39:16 +00:00
r600.bitcast.ll
r600.extract-lowbits.ll
AMDGPU: Stop trying to extend arguments for clover
2018-07-28 12:34:25 +00:00
r600.func-alignment.ll
AMDGPU/R600: Make sure functions are cacheline aligned
2018-05-31 04:08:08 +00:00
r600.global_atomics.ll
r600.private-memory.ll
r600.work-item-intrinsics.ll
AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS
2018-08-01 18:36:07 +00:00
r600cfg.ll
rcp_iflag.ll
[AMDGPU] Convert rcp to rcp_iflag
2018-06-27 15:33:33 +00:00
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
readlane_exec0.mir
README
reduce-build-vec-ext-to-ext-build-vec.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
reduction.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir
Shrink interval after moving copy in removePartialRedundancy
2018-06-18 17:16:39 +00:00
regcoal-subrange-join.mir
regcoalesce-cannot-join-failures.mir
RegisterCoalescer: Assume CR_Replace for SubRangeJoin
2019-01-08 23:22:18 +00:00
regcoalesce-dbg.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
RegisterCoalescer: Defer clearing implicit_def lanes
2019-01-08 23:10:47 +00:00
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
[RegisterCoalescer] Fix for assert in removePartialRedundancy
2018-08-23 17:28:33 +00:00
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
RenameIndependentSubregs: Fix handling of undef tied operands
2018-07-09 20:07:03 +00:00
reorder-stores.ll
reqd-work-group-size.ll
AMDGPU: Add pass to optimize reqd_work_group_size
2018-05-18 21:35:00 +00:00
ret_jump.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
ret.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
saddo.ll
salu-to-valu.ll
sampler-resource-id.ll
scalar_to_vector_v2x16.ll
[AMDGPU] Restored selection of scalar_to_vector (v2x16)
2018-11-19 19:58:13 +00:00
scalar_to_vector.ll
AMDGPU: Fix scalar_to_vector for v4i16/v4f16
2018-06-20 19:45:48 +00:00
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
sched-crash-dbg-value.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
schedule-regpressure-limit2.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
schedule-regpressure-limit3.ll
[AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler
2018-05-12 01:41:56 +00:00
schedule-regpressure-limit.ll
schedule-regpressure.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
schedule-vs-if-nested-loop-failure.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
scheduler-subrange-crash.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
scratch-buffer.ll
scratch-simple.ll
AMDGPU: Use an ABS32_LO relocation for SCRATCH_RSRC_DWORD1
2018-12-19 11:55:03 +00:00
sdiv.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
sdivrem24.ll
[AMDGPU] Convert rcp to rcp_iflag
2018-06-27 15:33:33 +00:00
sdivrem64.ll
sdwa-gfx9.mir
sdwa-op64-test.ll
[AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos
2018-12-03 13:04:54 +00:00
sdwa-ops.mir
[AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos
2018-12-03 13:04:54 +00:00
sdwa-peephole-instr.mir
sdwa-peephole.ll
AMDGPU: Fix various issues around the VirtReg2Value mapping
2018-11-30 22:55:29 +00:00
sdwa-preserve.mir
[AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.
2018-03-30 05:03:36 +00:00
sdwa-scalar-ops.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
sdwa-vop2-64bit.mir
select64.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
select-opt.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
select-undef.ll
Moved dag-combine-select-undef.ll into amdgpu. NFC.
2018-11-17 00:17:15 +00:00
select-vectors.ll
AMDGPU: Make v4i16/v4f16 legal
2018-06-15 15:15:46 +00:00
select.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
Check shouldReduceLoadWidth from SimplifySetCC
2018-10-31 21:24:30 +00:00
setcc-opt.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
setcc-sext.ll
setcc.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
sgpr-control-flow.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
sgpr-spill-wrong-stack-id.mir
AMDGPU: Cleanup / relax tests for future changes
2018-11-26 17:17:07 +00:00
sgprcopies.ll
shader-addr64-nonuniform.ll
[AMDGPU] Avoid using divergent value in mubuf addr64 descriptor
2018-08-02 22:53:57 +00:00
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
shl_add_constant.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
shl_add_ptr.ll
shl_add.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
shl_or.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
shl-add-to-add-shl.ll
shl.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
shl.v2i16.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-vop3-carry-out.mir
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
si-annotate-cfg-loop-assert.ll
si-fix-sgpr-copies.mir
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
2018-03-19 14:07:15 +00:00
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
si-scheduler.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
si-sgpr-spill.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
si-spill-cf.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
[AMDGPU] Disable SReg Global LD/ST, perf regression
2018-11-30 18:29:17 +00:00
si-vector-hang.ll
sibling-call.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
sign_extend.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
simplify-libcalls.ll
[AMDGPU] Fix discarded result of addAttribute
2018-12-09 21:56:50 +00:00
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
[AMDGPU] Add instruction selection for i1 to f16 conversion
2018-09-19 16:32:12 +00:00
skip-if-dead.ll
AMDGPU: Remove llvm.AMDGPU.kill
2018-12-07 17:46:16 +00:00
smed3.ll
AMDGPU: Additional pattern for i16 median3 matching
2018-11-14 20:10:41 +00:00
sminmax.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
sminmax.v2i16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
smrd-fold-offset.mir
AMDGPU: Divergence-driven selection of scalar buffer load intrinsics
2018-11-30 22:55:38 +00:00
smrd-vccz-bug.ll
AMDGPU/InsertWaitcnts: Untangle some semi-global state
2018-11-29 11:06:06 +00:00
smrd.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
sopk-compares.ll
spill-alloc-sgpr-init-bug.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
spill-before-exec.mir
[RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled
2018-09-25 18:37:38 +00:00
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll
AMDGPU: Move a flawed assert when spilling SGPRs
2018-04-23 16:13:30 +00:00
spill-empty-live-interval.mir
AMDGPU: Cleanup / relax tests for future changes
2018-11-26 17:17:07 +00:00
spill-m0.ll
RegAllocFast: Leave unassigned virtreg entries in map
2018-11-07 06:57:03 +00:00
spill-offset-calculation.ll
[AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits
2018-07-26 19:47:51 +00:00
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-wide-sgpr.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
split-scalar-i64-add.ll
CodeGen: Make computeRegisterLiveness consider successors
2018-08-30 07:17:51 +00:00
split-smrd.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
split-vector-memoperand-offsets.ll
splitkit.mir
sra.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
srem.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
srl.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
ssubo.ll
stack-realign.ll
AMDGPU: Support realigning stack
2018-03-29 21:30:06 +00:00
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
AMDGPU: Cleanup / relax tests for future changes
2018-11-26 17:17:07 +00:00
store_typed.ll
store-barrier.ll
store-global.ll
[AMDGPU] Fix dwordx3/southern-islands failures.
2019-01-10 16:21:08 +00:00
store-hi16.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
store-local.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
store-private.ll
AMDGPU: Stop trying to extend arguments for clover
2018-07-28 12:34:25 +00:00
store-v3i64.ll
[AMDGPU] Fix dwordx3/southern-islands failures.
2019-01-10 16:21:08 +00:00
store-vector-ptrs.ll
store-weird-sizes.ll
[SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts simplification
2018-12-01 12:08:55 +00:00
stress-calls.ll
Reapply "AMDGPU: Force inlining if LDS global address is used"
2018-07-10 14:03:41 +00:00
structurize1.ll
structurize.ll
sub_i1.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
sub.i16.ll
sub.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
sub.v2i16.ll
[AMDGPU] Remove useless check from test. NFC.
2018-09-25 01:24:54 +00:00
subreg_interference.mir
subreg-coalescer-crash.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir
[RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers
2018-12-14 14:07:57 +00:00
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll
AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as
2018-05-29 19:09:13 +00:00
trunc-bitcast-vector.ll
[AMDGPU] combine extractelement into several selects
2018-11-13 21:18:21 +00:00
trunc-cmp-constant.ll
trunc-combine.ll
[DAGCombiner] allow narrowing of add followed by truncate
2018-12-22 17:10:31 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
trunc-store.ll
trunc-vector-store-assertion-failure.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
trunc.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
tti-unroll-prefs.ll
twoaddr-mad.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
uaddo.ll
udiv.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
udivrem24.ll
[AMDGPU] Convert rcp to rcp_iflag
2018-06-27 15:33:33 +00:00
udivrem64.ll
udivrem.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
uitofp.f16.ll
[AMDGPU] Add instruction selection for i1 to f16 conversion
2018-09-19 16:32:12 +00:00
umed3.ll
AMDGPU: Additional pattern for i16 median3 matching
2018-11-14 20:10:41 +00:00
unaligned-load-store.ll
DAG: Fix expansion of unaligned FP loads and stores
2018-09-13 12:14:23 +00:00
undefined-physreg-sgpr-spill.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
undefined-subreg-liverange.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
[AMDGPU] Revert b0efc4fd6 ( https://reviews.llvm.org/D40556 )
2018-04-25 12:32:46 +00:00
unify-metadata.ll
unigine-liveness-crash.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
unknown-processor.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
unpack-half.ll
unroll.ll
unsupported-calls.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
unsupported-cc.ll
urem.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
use-sgpr-multiple-times.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
usubo.ll
v1i64-kernel-arg.ll
v_cndmask.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
v_mac.ll
v_madak_f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
v_swap_b32.mir
[AMDGPU] Match v_swap_b32
2018-10-29 17:26:01 +00:00
valu-i1.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
vccz-corrupt-bug-workaround.mir
AMDGPU/InsertWaitcnts: Untangle some semi-global state
2018-11-29 11:06:06 +00:00
vector-alloca-addrspacecast.ll
AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.
2018-05-11 22:17:57 +00:00
vector-alloca-atomic.ll
AMDGPU/SI: Don't promote alloca to vector for atomic load/store
2018-05-17 21:49:44 +00:00
vector-alloca.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
vector-extract-insert.ll
[AMDGPU] Convert insert_vector_elt into set of selects
2018-11-19 17:39:20 +00:00
vector-legalizer-divergence.ll
[CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands
2018-06-04 20:19:45 +00:00
vectorize-global-local.ll
verifier-implicit-virtreg-invalid-physreg-liveness.mir
MachineVerifier: Fix assert on implicit virtreg use
2018-08-27 17:40:09 +00:00
verifier-pseudo-terminators.mir
AMDGPU: Fix analyzeBranch failing with pseudoterminators
2018-11-16 05:03:02 +00:00
vertex-fetch-encoding.ll
vgpr-spill-emergency-stack-slot-compute.ll
AMDGPU: Enable code object v3 for AMDHSA only
2018-11-15 02:32:43 +00:00
vgpr-spill-emergency-stack-slot.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
vi-removed-intrinsics.ll
Reapply "Adapt gcov to changes in CFE."
2018-12-06 18:44:48 +00:00
vop-shrink-frame-index.mir
[MIR] Add support for debug metadata for fixed stack objects
2018-04-25 18:58:06 +00:00
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-back-edge-loop.mir
[AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks
2018-05-30 15:47:45 +00:00
waitcnt-debug.mir
[AMDGPU] Waitcnt pass: add debug options
2018-04-25 19:21:26 +00:00
waitcnt-flat.ll
waitcnt-loop-irreducible.mir
AMDGPU/InsertWaitcnts: Update VGPR/SGPR bounds when brackets are merged
2018-12-19 10:17:49 +00:00
waitcnt-loop-single-basic-block.mir
[AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed.
2018-03-14 22:04:32 +00:00
waitcnt-looptest.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
waitcnt-no-redundant.mir
waitcnt-permute.mir
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
2018-04-27 17:59:15 +00:00
waitcnt-preexisting.mir
AMDGPU/InsertWaitcnts: Untangle some semi-global state
2018-11-29 11:06:06 +00:00
waitcnt.mir
[AMDGPU][Waitcnt] Fix handling of flat instrs
2018-06-04 16:51:59 +00:00
wave_dispatch_regs.ll
[AMDGPU] Ensure there are enough registers for wave dispatch
2018-04-11 17:18:36 +00:00
widen_extending_scalar_loads.ll
AMDGPU: Preserve metadata when widening loads
2018-06-05 19:52:56 +00:00
widen-smrd-loads.ll
Regenerate test.
2019-01-07 12:20:35 +00:00
widen-vselect-and-mask.ll
wqm.ll
AMDGPU: Remove llvm.AMDGPU.kill
2018-12-07 17:46:16 +00:00
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
xfail.r600.bitcast.ll
xnor.ll
[AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XOR
2018-12-01 12:27:53 +00:00
xor_add.ll
AMDGPU: Generate VALU ThreeOp Integer instructions
2018-12-06 14:33:40 +00:00
xor.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
zero_extend.ll
AMDGPU: Stop trying to extend arguments for clover
2018-07-28 12:34:25 +00:00
zext-i64-bit-operand.ll
zext-lid.ll
[SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt
2018-10-31 19:57:36 +00:00
