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https://github.com/RPCS3/llvm-mirror.git
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5c65e3023e
This reverts commit e3e2923a39cbec3b3bc3a7d3f0e9a77a4115080e, svn revision rL350721 llvm-svn: 350730
186 lines
7.7 KiB
LLVM
186 lines
7.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-dpp-combine -verify-machineinstrs < %s | FileCheck %s
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; VOP2 with literal cannot be combined
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; CHECK-LABEL: {{^}}dpp_combine_i32_literal:
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; CHECK: v_mov_b32_dpp [[OLD:v[0-9]+]], {{v[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x2 bank_mask:0x1 bound_ctrl:0
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, vcc, 42, [[OLD]]
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define amdgpu_kernel void @dpp_combine_i32_literal(i32 addrspace(1)* %out, i32 %in) {
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 2, i32 1, i1 1) #0
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%res = add nsw i32 %dpp, 42
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_bz:
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; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_i32_bz(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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%res = add nsw i32 %dpp, %x
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_boff_undef:
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; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @dpp_combine_i32_boff_undef(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
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%res = add nsw i32 %dpp, %x
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_boff_0:
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; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_i32_boff_0(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
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%res = add nsw i32 %dpp, %x
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_boff_max:
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; CHECK: v_bfrev_b32_e32 [[OLD:v[0-9]+]], -2
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; CHECK: v_max_i32_dpp [[OLD]], {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @dpp_combine_i32_boff_max(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 2147483647, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
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%cmp = icmp sge i32 %dpp, %x
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%res = select i1 %cmp, i32 %dpp, i32 %x
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_boff_min:
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; CHECK: v_bfrev_b32_e32 [[OLD:v[0-9]+]], 1
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; CHECK: v_min_i32_dpp [[OLD]], {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @dpp_combine_i32_boff_min(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 -2147483648, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
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%cmp = icmp sle i32 %dpp, %x
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%res = select i1 %cmp, i32 %dpp, i32 %x
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_boff_mul:
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; CHECK: v_mul_i32_i24_dpp v0, v3, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @dpp_combine_i32_boff_mul(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 1, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
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%dpp.shl = shl i32 %dpp, 8
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%dpp.24 = ashr i32 %dpp.shl, 8
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%x.shl = shl i32 %x, 8
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%x.24 = ashr i32 %x.shl, 8
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%res = mul i32 %dpp.24, %x.24
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_commute:
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; CHECK: v_subrev_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_i32_commute(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 2, i32 1, i32 1, i1 1) #0
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%res = sub nsw i32 %x, %dpp
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_f32:
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; CHECK: v_add_f32_dpp {{v[0-9]+}}, {{v[0-9]+}}, v0 quad_perm:[3,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_f32(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 3, i32 1, i32 1, i1 1) #0
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%dpp.f32 = bitcast i32 %dpp to float
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%x.f32 = bitcast i32 %x to float
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%res.f32 = fadd float %x.f32, %dpp.f32
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%res = bitcast float %res.f32 to i32
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_test_f32_mods:
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; CHECK: v_mul_f32_dpp {{v[0-9]+}}, |{{v[0-9]+}}|, -v0 quad_perm:[0,1,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_test_f32_mods(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 4, i32 1, i32 1, i1 1) #0
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%x.f32 = bitcast i32 %x to float
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%x.f32.neg = fsub float -0.000000e+00, %x.f32
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%dpp.f32 = bitcast i32 %dpp to float
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%dpp.f32.cmp = fcmp fast olt float %dpp.f32, 0.000000e+00
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%dpp.f32.sign = select i1 %dpp.f32.cmp, float -1.000000e+00, float 1.000000e+00
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%dpp.f32.abs = fmul fast float %dpp.f32, %dpp.f32.sign
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%res.f32 = fmul float %x.f32.neg, %dpp.f32.abs
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%res = bitcast float %res.f32 to i32
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_mac:
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; CHECK: v_mac_f32_dpp v0, {{v[0-9]+}}, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_mac(float addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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%dpp.f32 = bitcast i32 %dpp to float
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%x.f32 = bitcast i32 %x to float
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%y.f32 = bitcast i32 %y to float
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%mult = fmul float %dpp.f32, %y.f32
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%res = fadd float %mult, %x.f32
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store float %res, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_sequence:
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define amdgpu_kernel void @dpp_combine_sequence(i32 addrspace(1)* %out, i32 %in, i1 %cmp) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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%resadd = add nsw i32 %dpp, %x
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br label %bb3
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bb2:
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; CHECK: v_subrev_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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%ressub = sub nsw i32 %x, %dpp
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br label %bb3
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bb3:
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%res = phi i32 [%resadd, %bb1], [%ressub, %bb2]
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_sequence_negative:
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; CHECK: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_sequence_negative(i32 addrspace(1)* %out, i32 %in, i1 %cmp) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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%resadd = add nsw i32 %dpp, %x
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br label %bb3
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bb2:
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%ressub = sub nsw i32 2, %dpp ; break seq
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br label %bb3
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bb3:
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%res = phi i32 [%resadd, %bb1], [%ressub, %bb2]
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.workitem.id.y()
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
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attributes #0 = { nounwind readnone convergent }
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