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40 lines
1.5 KiB
LLVM
40 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906
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declare i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 %clamp)
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; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_clamp
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; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_sdot4_clamp(
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i32 addrspace(1)* %r,
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<4 x i8> addrspace(1)* %a,
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<4 x i8> addrspace(1)* %b,
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i32 addrspace(1)* %c) {
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entry:
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%a.val = load <4 x i8>, <4 x i8> addrspace(1)* %a
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%b.val = load <4 x i8>, <4 x i8> addrspace(1)* %b
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%a.val.cast = bitcast <4 x i8> %a.val to i32
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%b.val.cast = bitcast <4 x i8> %b.val to i32
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%c.val = load i32, i32 addrspace(1)* %c
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%r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1)
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store i32 %r.val, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_no_clamp
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; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_sdot4_no_clamp(
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i32 addrspace(1)* %r,
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<4 x i8> addrspace(1)* %a,
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<4 x i8> addrspace(1)* %b,
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i32 addrspace(1)* %c) {
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entry:
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%a.val = load <4 x i8>, <4 x i8> addrspace(1)* %a
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%b.val = load <4 x i8>, <4 x i8> addrspace(1)* %b
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%a.val.cast = bitcast <4 x i8> %a.val to i32
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%b.val.cast = bitcast <4 x i8> %b.val to i32
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%c.val = load i32, i32 addrspace(1)* %c
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%r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0)
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store i32 %r.val, i32 addrspace(1)* %r
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ret void
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}
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