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46 lines
2.1 KiB
LLVM
46 lines
2.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s
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; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s
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; VI-LABEL: {{^}}dpp_test:
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; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
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; VI: v_mov_b32_e32 v1, s{{[0-9]+}}
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; VI-OPT: s_nop 1
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; VI-NOOPT: s_nop 0
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; VI-NOOPT: s_nop 0
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; VI: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]
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define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 1) #0
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store i32 %tmp0, i32 addrspace(1)* %out
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ret void
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}
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; VI-LABEL: {{^}}dpp_test1:
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; VI: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; VI-NEXT: s_nop 0
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; VI-NEXT: s_nop 0
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; VI-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
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@0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4
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define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds [448 x i32], [448 x i32] addrspace(3)* @0, i32 0, i32 %tmp
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%tmp3 = load i32, i32 addrspace(3)* %tmp2, align 4
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fence syncscope("workgroup") release
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tail call void @llvm.amdgcn.s.barrier()
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fence syncscope("workgroup") acquire
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%tmp4 = add nsw i32 %tmp3, %tmp3
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%tmp5 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp4, i32 177, i32 15, i32 15, i1 zeroext false)
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%tmp6 = add nsw i32 %tmp5, %tmp4
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%tmp7 = getelementptr inbounds i32, i32* %arg, i64 %tmp1
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store i32 %tmp6, i32* %tmp7, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare void @llvm.amdgcn.s.barrier()
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
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attributes #0 = { nounwind readnone convergent }
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