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2b0231f519
This replaces most argument uses with loads, but for now not all. The code in SelectionDAG for calling convention lowering is actively harmful for amdgpu_kernel. It attempts to split the argument types into register legal types, which results in low quality code for arbitary types. Since all kernel arguments are passed in memory, we just want the raw types. I've tried a couple of methods of mitigating this in SelectionDAG, but it's easier to just bypass this problem alltogether. It's possible to hack around the problem in the initial lowering, but the real problem is the DAG then expects to be able to use CopyToReg/CopyFromReg for uses of the arguments outside the block. Exposing the argument loads in the IR also has the advantage that the LoadStoreVectorizer can merge them. I'm not sure the best approach to dealing with the IR argument list is. The patch as-is just leaves the IR arguments in place, so all the existing code will still compute the same kernarg size and pointlessly lowers the arguments. Arguably the frontend should emit kernels with an empty argument list in the first place. Alternatively a dummy array could be inserted as a single argument just to reserve space. This does have some disadvantages. Local pointer kernel arguments can no longer have AssertZext placed on them as the equivalent !range metadata is not valid on pointer typed loads. This is mostly bad for SI which needs to know about the known bits in order to use the DS instruction offset, so in this case this is not done. More importantly, this skips noalias arguments since this pass does not yet convert this to the equivalent !alias.scope and !noalias metadata. Producing this metadata correctly seems to be tricky, although this logically is the same as inlining into a function which doesn't exist. Additionally, exposing these loads to the vectorizer may result in degraded aliasing information if a pointer load is merged with another argument load. I'm also not entirely sure this is preserving the current clover ABI, although I would greatly prefer if it would stop widening arguments and match the HSA ABI. As-is I think it is extending < 4-byte arguments to 4-bytes but doesn't align them to 4-bytes. llvm-svn: 335650
269 lines
8.5 KiB
LLVM
269 lines
8.5 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,FUNC %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
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; FUNC-LABEL: {{^}}test_umul24_i32:
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; GCN: v_mul_u32_u24
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define amdgpu_kernel void @test_umul24_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = lshr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = lshr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i16_sext:
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; SI: v_mul_u32_u24_e{{(32|64)}} [[VI_MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; SI: v_bfe_i32 v{{[0-9]}}, [[VI_MUL]], 0, 16
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; VI: s_mul_i32 [[MUL:s[0-9]+]]
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; VI: s_sext_i32_i16 s{{[0-9]+}}, [[MUL]]
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define amdgpu_kernel void @test_umul24_i16_sext(i32 addrspace(1)* %out, i16 %a, i16 %b) {
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entry:
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%mul = mul i16 %a, %b
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%ext = sext i16 %mul to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i16_vgpr_sext:
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; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; VI: v_mul_lo_u16_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 16
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define amdgpu_kernel void @test_umul24_i16_vgpr_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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%ptr_a = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.x
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%ptr_b = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.y
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%a = load i16, i16 addrspace(1)* %ptr_a
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%b = load i16, i16 addrspace(1)* %ptr_b
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%mul = mul i16 %a, %b
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%val = sext i16 %mul to i32
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i16:
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; SI: s_and_b32
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; SI: v_mul_u32_u24_e32
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; SI: v_and_b32_e32
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; VI: s_mul_i32
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; VI: s_and_b32
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define amdgpu_kernel void @test_umul24_i16(i32 addrspace(1)* %out, i16 %a, i16 %b) {
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entry:
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%mul = mul i16 %a, %b
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%ext = zext i16 %mul to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i16_vgpr:
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; SI: v_mul_u32_u24_e32
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; SI: v_and_b32_e32
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; VI: v_mul_lo_u16
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define amdgpu_kernel void @test_umul24_i16_vgpr(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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%ptr_a = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.x
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%ptr_b = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.y
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%a = load i16, i16 addrspace(1)* %ptr_a
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%b = load i16, i16 addrspace(1)* %ptr_b
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%mul = mul i16 %a, %b
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%val = zext i16 %mul to i32
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i8_vgpr:
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; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; VI: v_mul_lo_u16_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
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define amdgpu_kernel void @test_umul24_i8_vgpr(i32 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b) {
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entry:
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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%a.ptr = getelementptr i8, i8 addrspace(1)* %a, i32 %tid.x
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%b.ptr = getelementptr i8, i8 addrspace(1)* %b, i32 %tid.y
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%a.l = load i8, i8 addrspace(1)* %a.ptr
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%b.l = load i8, i8 addrspace(1)* %b.ptr
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%mul = mul i8 %a.l, %b.l
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%ext = sext i8 %mul to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umulhi24_i32_i64:
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; GCN-NOT: and
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; GCN: v_mul_hi_u32_u24_e32 [[RESULT:v[0-9]+]],
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; GCN-NEXT: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_umulhi24_i32_i64(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%a.24 = and i32 %a, 16777215
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%b.24 = and i32 %b, 16777215
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%a.24.i64 = zext i32 %a.24 to i64
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%b.24.i64 = zext i32 %b.24 to i64
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%mul48 = mul i64 %a.24.i64, %b.24.i64
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%mul48.hi = lshr i64 %mul48, 32
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%mul24hi = trunc i64 %mul48.hi to i32
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store i32 %mul24hi, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umulhi24:
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; GCN-NOT: and
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; GCN: v_mul_hi_u32_u24_e32 [[RESULT:v[0-9]+]],
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; GCN-NEXT: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_umulhi24(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%a.24 = and i64 %a, 16777215
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%b.24 = and i64 %b, 16777215
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%mul48 = mul i64 %a.24, %b.24
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%mul48.hi = lshr i64 %mul48, 32
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%mul24.hi = trunc i64 %mul48.hi to i32
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store i32 %mul24.hi, i32 addrspace(1)* %out
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ret void
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}
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; Multiply with 24-bit inputs and 64-bit output.
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; FUNC-LABEL: {{^}}test_umul24_i64:
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; GCN-NOT: and
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; GCN-NOT: lshr
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; GCN-DAG: v_mul_u32_u24_e32
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; GCN-DAG: v_mul_hi_u32_u24_e32
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @test_umul24_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%tmp0 = shl i64 %a, 40
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%a_24 = lshr i64 %tmp0, 40
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%tmp1 = shl i64 %b, 40
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%b_24 = lshr i64 %tmp1, 40
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%tmp2 = mul i64 %a_24, %b_24
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store i64 %tmp2, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i64_square:
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; GCN: s_load_dword [[A:s[0-9]+]]
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; GCN-NOT: s_and_b32
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; GCN-DAG: v_mul_hi_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
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; GCN-DAG: v_mul_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
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define amdgpu_kernel void @test_umul24_i64_square(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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entry:
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%tmp0 = shl i64 %a, 40
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%a.24 = lshr i64 %tmp0, 40
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%tmp2 = mul i64 %a.24, %a.24
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store i64 %tmp2, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umulhi16_i32:
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; GCN: s_and_b32
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; GCN: s_and_b32
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; GCN: v_mul_u32_u24_e32 [[MUL24:v[0-9]+]]
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; GCN: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[MUL24]]
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define amdgpu_kernel void @test_umulhi16_i32(i16 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%a.16 = and i32 %a, 65535
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%b.16 = and i32 %b, 65535
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%mul = mul i32 %a.16, %b.16
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%hi = lshr i32 %mul, 16
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%mulhi = trunc i32 %hi to i16
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store i16 %mulhi, i16 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umul24_i33:
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; GCN: s_load_dword s
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; GCN: s_load_dword s
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; GCN-NOT: and
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; GCN-NOT: lshr
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; GCN-DAG: v_mul_u32_u24_e32 v[[MUL_LO:[0-9]+]],
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; GCN-DAG: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
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; GCN-DAG: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[MUL_LO]]:[[HI]]{{\]}}
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define amdgpu_kernel void @test_umul24_i33(i64 addrspace(1)* %out, i33 %a, i33 %b) {
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entry:
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%tmp0 = shl i33 %a, 9
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%a_24 = lshr i33 %tmp0, 9
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%tmp1 = shl i33 %b, 9
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%b_24 = lshr i33 %tmp1, 9
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%tmp2 = mul i33 %a_24, %b_24
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%ext = zext i33 %tmp2 to i64
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store i64 %ext, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_umulhi24_i33:
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; GCN: s_load_dword s
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; GCN: s_load_dword s
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; GCN-NOT: and
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; GCN-NOT: lshr
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; GCN: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
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; GCN-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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; GCN-NEXT: buffer_store_dword v[[HI]]
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define amdgpu_kernel void @test_umulhi24_i33(i32 addrspace(1)* %out, i33 %a, i33 %b) {
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entry:
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%tmp0 = shl i33 %a, 9
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%a_24 = lshr i33 %tmp0, 9
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%tmp1 = shl i33 %b, 9
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%b_24 = lshr i33 %tmp1, 9
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%tmp2 = mul i33 %a_24, %b_24
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%hi = lshr i33 %tmp2, 32
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%trunc = trunc i33 %hi to i32
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store i32 %trunc, i32 addrspace(1)* %out
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ret void
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}
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; Make sure the created any_extend is ignored to use the real bits
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; being multiplied.
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; GCN-LABEL: {{^}}test_umul24_anyextend_i24_src0_src1:
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; GCN-DAG: v_mul_u32_u24_e32 v0, 0xea, v0
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; GCN-DAG: v_mul_u32_u24_e32 v1, 0x39b, v1
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; GCN: v_mul_u32_u24_e32 v0, v0, v1
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; GCN: v_and_b32_e32 v0, 0x1fffe, v0
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; GCN: v_mul_u32_u24_e32 v0, 0x63, v0
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; GCN: s_setpc_b64
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define i17 @test_umul24_anyextend_i24_src0_src1(i24 %a, i24 %b) {
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entry:
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%aa = mul i24 %a, 234
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%bb = mul i24 %b, 923
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%a_32 = zext i24 %aa to i32
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%b_32 = zext i24 %bb to i32
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%mul = mul i32 %a_32, %b_32
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%trunc = trunc i32 %mul to i17
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%arst = mul i17 %trunc, 99
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ret i17 %arst
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}
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; GCN-LABEL: {{^}}test_umul24_anyextend_i23_src0_src1:
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; GCN: s_mov_b32 [[U23_MASK:s[0-9]+]], 0x7fffff
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; GCN-DAG: v_and_b32_e32 v0, [[U23_MASK]], v0
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; GCN-DAG: v_and_b32_e32 v1, [[U23_MASK]], v1
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; GCN-DAG: v_mul_u32_u24_e32 v0, 0xea, v0
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; GCN-DAG: v_mul_u32_u24_e32 v1, 0x39b, v1
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; GCN: v_and_b32_e32 v1, s6, v1
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; GCN: v_and_b32_e32 v0, 0x7ffffe, v0
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; GCN: v_mul_u32_u24_e32 v0, v0, v1
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; GCN: v_and_b32_e32 v0, 0x1fffe, v0
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; GCN: v_mul_u32_u24_e32 v0, 0x63, v0
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; GCN: s_setpc_b64
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define i17 @test_umul24_anyextend_i23_src0_src1(i23 %a, i23 %b) {
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entry:
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%aa = mul i23 %a, 234
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%bb = mul i23 %b, 923
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%a_32 = zext i23 %aa to i32
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%b_32 = zext i23 %bb to i32
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%mul = mul i32 %a_32, %b_32
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%trunc = trunc i32 %mul to i17
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%arst = mul i17 %trunc, 99
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ret i17 %arst
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}
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