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2790a1e6e3
The spaces in the instructions are now consistent. llvm-svn: 326829
29 lines
837 B
LLVM
29 lines
837 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Generate MemOps for V4 and above.
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define void @f(i16* nocapture %p) nounwind {
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entry:
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; CHECK: memh(r{{[0-9]+}}+#20) -= #1
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%add.ptr = getelementptr inbounds i16, i16* %p, i32 10
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%0 = load i16, i16* %add.ptr, align 2
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%conv2 = zext i16 %0 to i32
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%sub = add nsw i32 %conv2, 65535
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%conv1 = trunc i32 %sub to i16
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store i16 %conv1, i16* %add.ptr, align 2
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ret void
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}
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define void @g(i16* nocapture %p, i32 %i) nounwind {
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entry:
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; CHECK: memh(r{{[0-9]+}}+#20) -= #1
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%add.ptr.sum = add i32 %i, 10
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%add.ptr1 = getelementptr inbounds i16, i16* %p, i32 %add.ptr.sum
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%0 = load i16, i16* %add.ptr1, align 2
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%conv3 = zext i16 %0 to i32
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%sub = add nsw i32 %conv3, 65535
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%conv2 = trunc i32 %sub to i16
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store i16 %conv2, i16* %add.ptr1, align 2
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ret void
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}
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