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llvm-mirror/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -march=hexagon -run-pass liveintervals -run-pass machineverifier -run-pass simple-register-coalescing %s -o - | FileCheck %s
#
# If there is no consumer of the live intervals, the live intervals pass
# will be freed immediately after it runs, before the verifier. Add a
# user (register coalescer in this case), so that the verification will
# cover live intervals as well.
#
# Make sure that this compiles successfully.
# CHECK: undef %1.isub_lo:doubleregs = A2_addi %1.isub_lo, 1
---
name: fred
tracksRegLiveness: true
registers:
- { id: 0, class: intregs }
- { id: 1, class: doubleregs }
- { id: 2, class: predregs }
- { id: 3, class: doubleregs }
body: |
bb.0:
liveins: $d0
successors: %bb.1
%0 = IMPLICIT_DEF
%1 = COPY $d0
bb.1:
successors: %bb.1
%2 = C2_cmpgt %0, %1.isub_lo
%3 = COPY %1
%1 = COPY %3
undef %1.isub_lo = A2_addi %1.isub_lo, 1
J2_jump %bb.1, implicit-def $pc
...