Alex Bradbury d56655b31e [RISCV] AsmParser support for the li pseudo instruction ... The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. The actual expansion to real instructions is similar to the expansion performed by the GNU Assembler. This patch supersedes D41949. Differential Revision: https://reviews.llvm.org/D46118 Patch by Mario Werner. llvm-svn: 334203		2018-06-07 15:35:47 +00:00
..
AsmParser	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
Disassembler	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
InstPrinter	[RISCV] Tablegen-driven Instruction Compression.	2018-04-06 21:07:05 +00:00
MCTargetDesc	Fix compilation of WebAssembly and RISCV after r334078	2018-06-06 10:57:50 +00:00
TargetInfo
CMakeLists.txt	[RISCV] Tablegen-driven Instruction Compression.	2018-04-06 21:07:05 +00:00
LLVMBuild.txt
RISCV.h
RISCV.td	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVAsmPrinter.cpp	Revert "[RISCV] implement li pseudo instruction"	2018-04-18 19:02:31 +00:00
RISCVCallingConv.td
RISCVFrameLowering.cpp	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVFrameLowering.h	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVInstrFormats.td	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVInstrInfo.h	[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot	2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
RISCVInstrInfoA.td
RISCVInstrInfoC.td	[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0	2018-04-12 19:22:40 +00:00
RISCVInstrInfoD.td	[RISCV] Codegen support for RV32D floating point comparison operations	2018-04-12 05:50:06 +00:00
RISCVInstrInfoF.td	[RISCV] Codegen support for RV32F floating point comparison operations	2018-03-21 15:11:02 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp	[RISCV] Add peepholes for Global Address lowering patterns	2018-05-29 19:34:54 +00:00
RISCVISelLowering.cpp	Set ADDE/ADDC/SUBE/SUBC to expand by default	2018-06-01 13:21:33 +00:00
RISCVISelLowering.h	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv	2018-04-12 05:34:25 +00:00
RISCVMCInstLower.cpp	[RISCV] Add codegen for RV32F floating point load/store	2018-03-20 13:26:12 +00:00
RISCVRegisterInfo.cpp	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.h	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVTargetMachine.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00