Alex Bradbury d56655b31e [RISCV] AsmParser support for the li pseudo instruction ... The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. The actual expansion to real instructions is similar to the expansion performed by the GNU Assembler. This patch supersedes D41949. Differential Revision: https://reviews.llvm.org/D46118 Patch by Mario Werner. llvm-svn: 334203		2018-06-07 15:35:47 +00:00
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AArch64	[AArch64][SVE] Fix range for DUP immediates (16bit elts)	2018-06-04 07:24:23 +00:00
AMDGPU	AMDGPU: Fix v_dot{4, 8}* instruction encoding	2018-05-15 19:32:47 +00:00
ARM	Fix the test case that places intermediate in source directory.	2018-06-06 18:53:17 +00:00
AsmParser	[MC] Add assembler support for .cg_profile.	2018-06-02 16:33:01 +00:00
AVR
BPF
COFF	[CodeView] Add prefix to CodeView registers.	2018-05-29 14:35:34 +00:00
Disassembler	[X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 are used as the index.	2018-06-06 19:15:15 +00:00
ELF	[MC] Add assembler support for .cg_profile.	2018-06-02 16:33:01 +00:00
Hexagon	[Hexagon] Use addAliasForDirective for data directives	2018-05-17 13:21:18 +00:00
Lanai
MachO	[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.	2018-05-09 02:40:45 +00:00
Mips	[mips] Partially revert r334031	2018-06-06 10:54:30 +00:00
PowerPC	[PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores	2018-05-28 15:27:58 +00:00
RISCV	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
Sparc	Implemented sane default for llvm-objdump's relocation Value format	2018-06-01 05:31:58 +00:00
SystemZ
WebAssembly	[WebAssembly] MC: Add compile-twice test and fix corresponding bug	2018-05-30 02:57:20 +00:00
X86	[MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixup	2018-06-06 09:40:06 +00:00