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d56655b31e
llvm-mirror/test/MC/RISCV
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Alex Bradbury d56655b31e [RISCV] AsmParser support for the li pseudo instruction 
The implementation follows the MIPS backend and expands the pseudo instruction 
directly during asm parsing. As the result, only real MC instructions are 
emitted to the MCStreamer. The actual expansion to real instructions is 
similar to the expansion performed by the GNU Assembler.

This patch supersedes D41949.

Differential Revision: https://reviews.llvm.org/D46118
Patch by Mario Werner.

llvm-svn: 334203
2018-06-07 15:35:47 +00:00
..
cnop.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-cjal.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-rv32d.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-rv32f.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-rv32i.s [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0 2018-04-12 19:22:40 +00:00
compress-rv64i.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compressed-relocations.s [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced 2018-05-18 06:42:21 +00:00
csr-aliases.s [RISCV] Pass MCSubtargetInfo to print methods. 2018-01-12 02:27:00 +00:00
data-directives-invalid.s [RISCV] Add support for .half, .hword, .word, .dword directives 2018-05-17 05:58:08 +00:00
data-directives-valid.s [RISCV] Add support for .half, .hword, .word, .dword directives 2018-05-17 05:58:08 +00:00
elf-flags.s [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
elf-header.s [RISCV] Bugfix createRISCVELFObjectWriter 2017-10-18 16:11:31 +00:00
fixups-compressed.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
fixups-diagnostics.s [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
fixups-expr.s [RISCV] Add symbol diff relocation support for RISC-V 2018-05-23 12:36:18 +00:00
fixups.s [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table 2018-05-30 01:16:36 +00:00
function-call-invalid.s [RISCV] Support "call" pseudoinstruction in the MC layer 2018-04-25 14:18:55 +00:00
function-call.s [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table 2018-05-30 01:16:36 +00:00
hilo-constaddr-expr.s [RISCV] Add symbol diff relocation support for RISC-V 2018-05-23 12:36:18 +00:00
hilo-constaddr.s [RISCV] Add symbol diff relocation support for RISC-V 2018-05-23 12:36:18 +00:00
linker-relaxation.s [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table 2018-05-30 01:16:36 +00:00
lit.local.cfg
option-invalid.s [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
option-rvc.s [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
priv-invalid.s [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools 2017-12-13 12:46:55 +00:00
priv-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
relocations.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
rv32-relaxation.s [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced 2018-05-18 06:42:21 +00:00
rv32a-invalid.s [RISCV] MC layer support for the standard RV64A instruction set extension 2017-12-07 10:59:12 +00:00
rv32a-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32c-aliases-valid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
rv32c-invalid.s [RISCV] Implement c.lui immediate operand constraint 2018-02-22 15:02:28 +00:00
rv32c-only-valid.s [RISCV] Update MC compression tests 2018-04-06 18:27:45 +00:00
rv32c-valid.s [RISCV] Implement c.lui immediate operand constraint 2018-02-22 15:02:28 +00:00
rv32d-invalid.s [RISCV] MC layer support for the standard RV32D instruction set extension 2017-12-07 10:46:23 +00:00
rv32d-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32dc-invalid.s [RISCV] MC layer support for the remaining RVC instructions 2017-12-13 09:32:55 +00:00
rv32dc-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv32f-invalid.s [RISCV] MC layer support for the standard RV64F instruction set extension 2017-12-07 11:02:55 +00:00
rv32f-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32fc-invalid.s [RISCV] MC layer support for the remaining RVC instructions 2017-12-13 09:32:55 +00:00
rv32fc-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv32i-aliases-invalid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
rv32i-aliases-valid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
rv32i-invalid.s [RISCV] Add support for %pcrel_lo. 2018-02-06 00:55:23 +00:00
rv32i-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32m-invalid.s [RISCV] MC layer support for the standard RV64M instruction set extension 2017-12-07 10:56:07 +00:00
rv32m-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64-relaxation.s [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced 2018-05-18 06:42:21 +00:00
rv64a-invalid.s [RISCV] MC layer support for the standard RV64A instruction set extension 2017-12-07 10:59:12 +00:00
rv64a-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64c-aliases-valid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
rv64c-invalid.s [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero 2017-12-15 10:20:51 +00:00
rv64c-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv64d-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64d-invalid.s [RISCV] Add missed tests for RV64D MC layer support 2017-12-07 11:05:38 +00:00
rv64d-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64dc-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv64f-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64f-invalid.s [RISCV] MC layer support for the standard RV64F instruction set extension 2017-12-07 11:02:55 +00:00
rv64f-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64i-aliases-invalid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
rv64i-aliases-valid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
rv64i-invalid.s [RISCV] MC layer support for the standard RV64I instructions 2017-12-07 10:53:48 +00:00
rv64i-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64m-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rvd-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rvf-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rvi-aliases-valid.s [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
tail-call-invalid.s [RISCV] Implement MC layer support for the tail pseudoinstruction 2018-05-17 17:31:27 +00:00
tail-call.s [RISCV] Implement MC layer support for the tail pseudoinstruction 2018-05-17 17:31:27 +00:00