mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
2e8acd83fd
This patch revamps the RegStackifier pass with a new tree traversal mechanism, enabling three major new features: - Stackification of values with multiple uses, using the result value of set_local - More aggressive stackification of instructions with side effects - Reordering operands in commutative instructions to enable more stackification. llvm-svn: 259009
62 lines
2.2 KiB
C++
62 lines
2.2 KiB
C++
//=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
///
|
|
/// \file
|
|
/// \brief This file contains the WebAssembly implementation of the
|
|
/// TargetInstrInfo class.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
|
|
#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
|
|
|
|
#include "WebAssemblyRegisterInfo.h"
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
#define GET_INSTRINFO_HEADER
|
|
#include "WebAssemblyGenInstrInfo.inc"
|
|
|
|
namespace llvm {
|
|
|
|
class WebAssemblySubtarget;
|
|
|
|
class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
|
|
const WebAssemblyRegisterInfo RI;
|
|
|
|
public:
|
|
explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
|
|
|
|
const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
|
|
|
|
bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
|
|
AliasAnalysis *AA) const override;
|
|
|
|
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
DebugLoc DL, unsigned DestReg, unsigned SrcReg,
|
|
bool KillSrc) const override;
|
|
MachineInstr *commuteInstructionImpl(MachineInstr *MI, bool NewMI,
|
|
unsigned OpIdx1,
|
|
unsigned OpIdx2) const override;
|
|
|
|
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify = false) const override;
|
|
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
|
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
|
DebugLoc DL) const override;
|
|
bool
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|