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https://github.com/RPCS3/llvm-mirror.git
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a636185af1
Summary: Adds an option -esan-assume-intra-cache-line which causes esan to assume that a single memory access touches just one cache line, even if it is not aligned, for better performance at a potential accuracy cost. Experiments show that the performance difference can be 2x or more, and accuracy loss is typically negligible, so we turn this on by default. This currently applies just to the working set tool. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, llvm-commits Differential Revision: http://reviews.llvm.org/D20978 llvm-svn: 271743
126 lines
4.0 KiB
LLVM
126 lines
4.0 KiB
LLVM
; Test EfficiencySanitizer working set instrumentation without aggressive
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; optimization flags.
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;
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; RUN: opt < %s -esan -esan-working-set -esan-assume-intra-cache-line=0 -S | FileCheck %s
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Intra-cache-line
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define i8 @aligned1(i8* %a) {
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entry:
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%tmp1 = load i8, i8* %a, align 1
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ret i8 %tmp1
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; CHECK: @llvm.global_ctors = {{.*}}@esan.module_ctor
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; CHECK: %0 = ptrtoint i8* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i8, i8* %a, align 1
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; CHECK-NEXT: ret i8 %tmp1
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}
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define i16 @aligned2(i16* %a) {
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entry:
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%tmp1 = load i16, i16* %a, align 2
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ret i16 %tmp1
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; CHECK: %0 = ptrtoint i16* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i16, i16* %a, align 2
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; CHECK-NEXT: ret i16 %tmp1
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}
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define i32 @aligned4(i32* %a) {
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entry:
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%tmp1 = load i32, i32* %a, align 4
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ret i32 %tmp1
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; CHECK: %0 = ptrtoint i32* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i32, i32* %a, align 4
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; CHECK-NEXT: ret i32 %tmp1
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}
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define i64 @aligned8(i64* %a) {
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entry:
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%tmp1 = load i64, i64* %a, align 8
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ret i64 %tmp1
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; CHECK: %0 = ptrtoint i64* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i64, i64* %a, align 8
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; CHECK-NEXT: ret i64 %tmp1
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Not guaranteed to be intra-cache-line
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define i16 @unaligned2(i16* %a) {
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entry:
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%tmp1 = load i16, i16* %a, align 1
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ret i16 %tmp1
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; CHECK: %0 = bitcast i16* %a to i8*
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; CHECK-NEXT: call void @__esan_unaligned_load2(i8* %0)
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; CHECK-NEXT: %tmp1 = load i16, i16* %a, align 1
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; CHECK-NEXT: ret i16 %tmp1
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}
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define i32 @unaligned4(i32* %a) {
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entry:
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%tmp1 = load i32, i32* %a, align 2
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ret i32 %tmp1
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; CHECK: %0 = bitcast i32* %a to i8*
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; CHECK-NEXT: call void @__esan_unaligned_load4(i8* %0)
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; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 2
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; CHECK-NEXT: ret i32 %tmp1
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}
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define i64 @unaligned8(i64* %a) {
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entry:
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%tmp1 = load i64, i64* %a, align 4
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ret i64 %tmp1
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; CHECK: %0 = bitcast i64* %a to i8*
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; CHECK-NEXT: call void @__esan_unaligned_load8(i8* %0)
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; CHECK-NEXT: %tmp1 = load i64, i64* %a, align 4
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; CHECK-NEXT: ret i64 %tmp1
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}
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