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c63f0c139e
The code in fixLdsBranchVmemWARHazard looks for patterns of a vmem/lds access followed by a branch, followed by an lds/vmem access. The handling of the hazard requires an arbitrary number of instructions to process. In the worst case where a function has a vmem access, but no lds accesses, all instructions are examined only to conclude that the hazard cannot occur. Add the pre-processing stage which detects if there is both lds and vmem present in the function and only then does the more costly search. This patch significantly improves compilation time in the cases the hazard cannot happen. In one pathological case I looked at IsHazardInst is needlesly called 88.6 milions times. The numbers could also be improved by introducing a map around the inner calls to ::getWaitStatesSince in fixLdsBranchVmemWARHazard, but nothing will beat not running fixLdsBranchVmemWARHazard at all in the cases detected by shouldRunLdsBranchVmemWARHazardFixup(). Differential Revision: https://reviews.llvm.org/D104219
122 lines
4.2 KiB
C++
122 lines
4.2 KiB
C++
//===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling on GCN processors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include <list>
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namespace llvm {
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class MachineFunction;
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class ScheduleDAG;
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class SIInstrInfo;
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class SIRegisterInfo;
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class GCNSubtarget;
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class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
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public:
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typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
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private:
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// Distinguish if we are called from scheduler or hazard recognizer
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bool IsHazardRecognizerMode;
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// This variable stores the instruction that has been emitted this cycle. It
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// will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
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// called.
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MachineInstr *CurrCycleInstr;
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std::list<MachineInstr*> EmittedInstrs;
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const MachineFunction &MF;
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const GCNSubtarget &ST;
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const SIInstrInfo &TII;
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const SIRegisterInfo &TRI;
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TargetSchedModel TSchedModel;
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bool RunLdsBranchVmemWARHazardFixup;
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/// RegUnits of uses in the current soft memory clause.
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BitVector ClauseUses;
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/// RegUnits of defs in the current soft memory clause.
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BitVector ClauseDefs;
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void resetClause() {
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ClauseUses.reset();
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ClauseDefs.reset();
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}
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void addClauseInst(const MachineInstr &MI);
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// Advance over a MachineInstr bundle. Look for hazards in the bundled
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// instructions.
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void processBundle();
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int getWaitStatesSince(IsHazardFn IsHazard, int Limit);
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int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit);
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int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit);
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int checkSoftClauseHazards(MachineInstr *SMEM);
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int checkSMRDHazards(MachineInstr *SMRD);
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int checkVMEMHazards(MachineInstr* VMEM);
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int checkDPPHazards(MachineInstr *DPP);
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int checkDivFMasHazards(MachineInstr *DivFMas);
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int checkGetRegHazards(MachineInstr *GetRegInstr);
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int checkSetRegHazards(MachineInstr *SetRegInstr);
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int createsVALUHazard(const MachineInstr &MI);
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int checkVALUHazards(MachineInstr *VALU);
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int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
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int checkRWLaneHazards(MachineInstr *RWLane);
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int checkRFEHazards(MachineInstr *RFE);
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int checkInlineAsmHazards(MachineInstr *IA);
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int checkReadM0Hazards(MachineInstr *SMovRel);
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int checkNSAtoVMEMHazard(MachineInstr *MI);
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int checkFPAtomicToDenormModeHazard(MachineInstr *MI);
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void fixHazards(MachineInstr *MI);
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bool fixVcmpxPermlaneHazards(MachineInstr *MI);
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bool fixVMEMtoScalarWriteHazards(MachineInstr *MI);
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bool fixSMEMtoVectorWriteHazards(MachineInstr *MI);
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bool fixVcmpxExecWARHazard(MachineInstr *MI);
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bool fixLdsBranchVmemWARHazard(MachineInstr *MI);
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int checkMAIHazards(MachineInstr *MI);
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int checkMAIHazards908(MachineInstr *MI);
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int checkMAIHazards90A(MachineInstr *MI);
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int checkMAIVALUHazards(MachineInstr *MI);
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int checkMAILdStHazards(MachineInstr *MI);
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public:
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GCNHazardRecognizer(const MachineFunction &MF);
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// We can only issue one instruction per cycle.
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bool atIssueLimit() const override { return true; }
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void EmitInstruction(SUnit *SU) override;
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void EmitInstruction(MachineInstr *MI) override;
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HazardType getHazardType(SUnit *SU, int Stalls) override;
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void EmitNoop() override;
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unsigned PreEmitNoops(MachineInstr *) override;
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unsigned PreEmitNoopsCommon(MachineInstr *);
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void AdvanceCycle() override;
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void RecedeCycle() override;
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bool ShouldPreferAnother(SUnit *SU) override;
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void Reset() override;
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};
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} // end namespace llvm
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#endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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