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AsmParser
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[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
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2021-07-22 10:42:15 +09:00 |
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Disassembler
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[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
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2021-07-22 10:42:15 +09:00 |
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MCTargetDesc
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[AMDGPU] Handle s_branch to another section.
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2021-07-13 12:17:47 +01:00 |
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TargetInfo
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Utils
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[AMDGPU] Allow frontends to disable null export for pixel shaders
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2021-07-22 10:20:46 +09:00 |
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AMDGPU.h
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[AMDGPU] Deduce attributes with the Attributor
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2021-07-24 06:07:15 +03:00 |
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AMDGPU.td
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[AMDGPU] Add maximum NSA size limit ISA feature
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2021-07-23 16:16:06 +09:00 |
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AMDGPUAliasAnalysis.cpp
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AMDGPUAliasAnalysis.h
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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[OpaquePtr] Clean up some uses of Type::getPointerElementType()
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2021-05-31 09:54:57 -07:00 |
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AMDGPUArgumentUsageInfo.cpp
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[GlobalISel] NFC: Change LLT::vector to take ElementCount.
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2021-06-24 11:26:12 +01:00 |
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AMDGPUArgumentUsageInfo.h
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AMDGPUAsmPrinter.cpp
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[AMDGPU] Improve register computation for indirect calls
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2021-07-20 13:48:50 +02:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU] Improve register computation for indirect calls
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2021-07-20 13:48:50 +02:00 |
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AMDGPUAtomicOptimizer.cpp
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AMDGPUAttributor.cpp
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[llvm] Inline getAssociatedFunction() in LLVM_DEBUG.
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2021-07-24 11:49:21 +02:00 |
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AMDGPUCallingConv.td
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AMDGPU: Promote signext/zeroext i16 shader returns
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2021-07-13 11:04:51 -04:00 |
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AMDGPUCallLowering.cpp
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AMDGPU/GlobalISel: Preserve more memory types
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2021-07-16 08:57:26 -04:00 |
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AMDGPUCallLowering.h
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AMDGPU/GlobalISel: Redo kernel argument load handling
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2021-07-16 08:56:54 -04:00 |
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AMDGPUCodeGenPrepare.cpp
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[AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask
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2021-06-18 13:04:12 -06:00 |
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AMDGPUCombine.td
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AMDGPUExportClustering.cpp
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AMDGPUExportClustering.h
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AMDGPUFeatures.td
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AMDGPUFixFunctionBitcasts.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUGenRegisterBankInfo.def
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AMDGPUGISel.td
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AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9
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2021-07-27 15:56:42 -04:00 |
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AMDGPUGlobalISelUtils.cpp
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AMDGPUGlobalISelUtils.h
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[ADT] Move DenseMapInfo for ArrayRef/StringRef into respective headers (NFC)
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2021-06-03 18:34:36 +02:00 |
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPUHSAMetadataStreamer.h
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AMDGPUInstCombineIntrinsic.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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AMDGPU: Move zeroed FP high bits optimization to patterns
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2021-06-22 12:47:56 -04:00 |
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AMDGPUInstructions.td
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[AMDGPU] Simplify tablegen files. NFC.
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2021-07-07 09:19:23 +01:00 |
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AMDGPUInstructionSelector.cpp
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPUInstructionSelector.h
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPUISelDAGToDAG.cpp
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AMDGPU: Fix high 16-bit optimization on gfx9
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2021-06-22 13:16:45 -04:00 |
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AMDGPUISelLowering.cpp
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[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
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2021-07-05 10:33:23 +01:00 |
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AMDGPUISelLowering.h
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPULateCodeGenPrepare.cpp
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[OpaquePtr] Remove uses of CreateConstGEP1_64() without element type
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2021-07-17 16:43:20 +02:00 |
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AMDGPULegalizerInfo.cpp
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[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
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2021-07-26 14:27:30 +01:00 |
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AMDGPULegalizerInfo.h
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[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
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2021-07-26 14:27:30 +01:00 |
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AMDGPULibCalls.cpp
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[llvm] Rename StringRef _lower() method calls to _insensitive()
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2021-06-25 00:22:01 +03:00 |
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AMDGPULibFunc.cpp
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[amdgpu] Add -enable-ocl-mangling-mismatch-workaround.
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2021-06-08 15:42:27 -04:00 |
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AMDGPULibFunc.h
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AMDGPULowerIntrinsics.cpp
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AMDGPULowerKernelArguments.cpp
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[CodeGen] Add missing includes (NFC)
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2021-06-06 15:48:27 +02:00 |
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AMDGPULowerKernelAttributes.cpp
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[AMDGPU] Fix pass name of AMDGPULowerKernelAttributes. NFC.
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2021-07-06 15:03:31 -07:00 |
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AMDGPULowerModuleLDSPass.cpp
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[AMDGPU] Disable LDS lowering for GFX shaders
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2021-07-20 02:55:25 -07:00 |
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AMDGPUMachineCFGStructurizer.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMachineModuleInfo.cpp
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AMDGPUMachineModuleInfo.h
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AMDGPUMacroFusion.cpp
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AMDGPUMacroFusion.h
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AMDGPUMCInstLower.cpp
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[amdgpu] Add 64-bit PC support when expanding unconditional branches.
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2021-07-26 14:50:30 -04:00 |
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AMDGPUMIRFormatter.cpp
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AMDGPUMIRFormatter.h
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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AMDGPUPerfHintAnalysis.cpp
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[AMDGPU] Tune perfhint analysis to account access width
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2021-07-21 12:46:10 -07:00 |
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AMDGPUPerfHintAnalysis.h
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[AMDGPU] Tune perfhint analysis to account access width
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2021-07-21 12:46:10 -07:00 |
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AMDGPUPostLegalizerCombiner.cpp
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AMDGPUPreLegalizerCombiner.cpp
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[GISel] Support llvm.memcpy.inline
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2021-06-30 12:39:05 -07:00 |
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AMDGPUPrintfRuntimeBinding.cpp
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[AMDGPU] Simplify GEP construction (NFC)
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2021-07-08 21:21:43 +02:00 |
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AMDGPUPromoteAlloca.cpp
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[OpaquePtr] Create API to make a copy of a PointerType with some address space
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2021-06-01 16:52:32 -07:00 |
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AMDGPUPropagateAttributes.cpp
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Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees"
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2021-06-24 02:33:50 +01:00 |
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AMDGPUPTNote.h
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AMDGPURegBankCombiner.cpp
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AMDGPURegisterBankInfo.cpp
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPURegisterBankInfo.h
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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AMDGPURegisterBanks.td
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[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
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2021-06-24 12:41:22 +09:00 |
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AMDGPUReplaceLDSUseWithPointer.cpp
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[OpaquePtr] Remove uses of CreateGEP() without element type
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2021-07-17 22:56:27 +02:00 |
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AMDGPUResourceUsageAnalysis.cpp
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[AMDGPU] Improve register computation for indirect calls
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2021-07-20 13:48:50 +02:00 |
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AMDGPUResourceUsageAnalysis.h
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[AMDGPU] Fix running ResourceUsageAnalysis
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2021-07-23 09:25:15 +02:00 |
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AMDGPURewriteOutArguments.cpp
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AMDGPUSearchableTables.td
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AMDGPUSubtarget.cpp
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[AMDGPU] Add maximum NSA size limit ISA feature
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2021-07-23 16:16:06 +09:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
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2021-07-05 10:33:23 +01:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Deduce attributes with the Attributor
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2021-07-24 06:07:15 +03:00 |
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AMDGPUTargetMachine.h
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AMDGPUTargetObjectFile.cpp
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AMDGPUTargetObjectFile.h
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AMDGPUTargetTransformInfo.cpp
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[Analysis] Add simple cost model for strict (in-order) reductions
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2021-07-26 10:26:06 +01:00 |
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AMDGPUTargetTransformInfo.h
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[Analysis] Add simple cost model for strict (in-order) reductions
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2021-07-26 10:26:06 +01:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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[AMDGPU] Don't handle export done when unify exit nodes
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2021-07-14 14:54:37 +08:00 |
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AMDGPUUnifyMetadata.cpp
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AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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BUFInstructions.td
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[AMDGPU] Simplify tablegen files. NFC.
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2021-07-07 09:19:23 +01:00 |
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CaymanInstructions.td
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CMakeLists.txt
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[AMDGPU] Deduce attributes with the Attributor
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2021-07-24 06:07:15 +03:00 |
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DSInstructions.td
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[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
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2021-06-16 12:23:29 +01:00 |
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EvergreenInstructions.td
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EXPInstructions.td
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FLATInstructions.td
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[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
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2021-06-16 12:23:29 +01:00 |
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GCNDPPCombine.cpp
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GCNHazardRecognizer.cpp
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[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
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2021-06-14 22:30:23 +02:00 |
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GCNHazardRecognizer.h
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[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
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2021-06-14 22:30:23 +02:00 |
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GCNILPSched.cpp
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GCNIterativeScheduler.cpp
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GCNIterativeScheduler.h
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GCNMinRegStrategy.cpp
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GCNNSAReassign.cpp
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GCNPreRAOptimizations.cpp
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
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2021-06-30 11:45:38 -07:00 |
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GCNProcessors.td
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[AMDGPU] Add gfx1035 target
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2021-06-24 14:32:41 -04:00 |
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GCNRegPressure.cpp
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GCNRegPressure.h
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GCNSchedStrategy.cpp
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GCNSchedStrategy.h
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GCNSubtarget.h
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[AMDGPU] Add maximum NSA size limit ISA feature
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2021-07-23 16:16:06 +09:00 |
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InstCombineTables.td
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MIMGInstructions.td
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[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
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2021-07-22 10:42:15 +09:00 |
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R600.td
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R600AsmPrinter.cpp
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R600AsmPrinter.h
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600FrameLowering.h
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
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R600ISelLowering.cpp
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R600ISelLowering.h
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[llvm][sve] Lowering for VLS truncating stores
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2021-07-23 14:04:55 +01:00 |
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OpenCLImageTypeLoweringPass.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600Processors.td
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600Subtarget.h
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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[AMDGPU] Set LoopInfo as preserved by SIAnnotateControlFlow
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2021-07-08 09:34:43 -07:00 |
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SIDefines.h
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SIFixSGPRCopies.cpp
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SIFixVGPRCopies.cpp
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SIFoldOperands.cpp
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AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
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2021-06-22 13:42:49 -04:00 |
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SIFormMemoryClauses.cpp
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SIFrameLowering.cpp
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[AMDGPU] Init scratch only if necessary
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2021-07-14 10:45:22 +02:00 |
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SIFrameLowering.h
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SIInsertHardClauses.cpp
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SIInsertWaitcnts.cpp
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SIInstrFormats.td
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SIInstrInfo.cpp
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[amdgpu] Add 64-bit PC support when expanding unconditional branches.
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2021-07-26 14:50:30 -04:00 |
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SIInstrInfo.h
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[amdgpu] Add 64-bit PC support when expanding unconditional branches.
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2021-07-26 14:50:30 -04:00 |
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SIInstrInfo.td
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AMDGPU: Move zeroed FP high bits optimization to patterns
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2021-06-22 12:47:56 -04:00 |
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SIInstructions.td
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[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
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2021-07-13 12:15:08 +02:00 |
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SIISelLowering.cpp
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[AMDGPU] Add SelectionDAG support for insert_subvector on v4f64
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2021-07-27 10:11:34 +09:00 |
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SIISelLowering.h
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[AMDGPU] NFC refactoring in isel for buffer access intrinsics
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2021-07-21 11:12:49 +01:00 |
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SILateBranchLowering.cpp
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[AMDGPU] Allow frontends to disable null export for pixel shaders
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2021-07-22 10:20:46 +09:00 |
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SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
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[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
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2021-07-13 12:15:08 +02:00 |
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SILowerI1Copies.cpp
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AMDGPU: Treat IMPLICIT_DEF like a constant lanemask source
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2021-07-27 11:44:38 -04:00 |
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SILowerSGPRSpills.cpp
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RegAlloc: Allow targets to split register allocation
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2021-07-13 18:49:29 -04:00 |
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SIMachineFunctionInfo.cpp
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[AMDGPU] Init scratch only if necessary
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2021-07-14 10:45:22 +02:00 |
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SIMachineFunctionInfo.h
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SIMachineScheduler.cpp
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SIMachineScheduler.h
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SIMemoryLegalizer.cpp
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[AMDGPU] Update gfx90a memory model support
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2021-06-30 04:05:22 +00:00 |
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SIModeRegister.cpp
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SIOptimizeExecMasking.cpp
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SIOptimizeExecMaskingPreRA.cpp
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SIOptimizeVGPRLiveRange.cpp
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[AMDGPU] Improve killed check for vgpr optimization
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2021-07-21 15:24:59 +02:00 |
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SIPeepholeSDWA.cpp
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SIPostRABundler.cpp
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SIPreAllocateWWMRegs.cpp
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SIPreEmitPeephole.cpp
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SIProgramInfo.cpp
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SIProgramInfo.h
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SIRegisterInfo.cpp
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[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
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2021-07-22 10:42:15 +09:00 |
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SIRegisterInfo.h
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RegAlloc: Allow targets to split register allocation
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2021-07-13 18:49:29 -04:00 |
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SIRegisterInfo.td
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[AMDGPU] Tidy SReg/SGPR definitions using template class
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2021-07-17 11:26:46 +09:00 |
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SISchedule.td
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Revert "[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions."
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2021-07-07 20:48:42 -07:00 |
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SIShrinkInstructions.cpp
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[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
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2021-07-22 10:42:15 +09:00 |
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SIWholeQuadMode.cpp
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SMInstructions.td
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[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
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2021-06-16 12:23:29 +01:00 |
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SOPInstructions.td
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[AMDGPU][MC] Added missing isCall/isBranch flags
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2021-07-16 14:59:10 +03:00 |
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VIInstrFormats.td
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VOP1Instructions.td
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[AMDGPU] Mark all relevant VOP1 instructions rematerializable
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2021-07-21 14:05:32 -07:00 |
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VOP2Instructions.td
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[AMDGPU] Mark relevant rematerializable VOP2 instructions
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2021-07-21 14:24:59 -07:00 |
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VOP3Instructions.td
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[AMDGPU] Mark relevant rematerializable VOP3 instructions
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2021-07-21 14:44:13 -07:00 |
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VOP3PInstructions.td
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[AMDGPU] Set VOP3P flag on Real instructions
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2021-06-16 15:00:45 +01:00 |
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VOPCInstructions.td
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[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
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2021-06-16 13:36:02 +01:00 |
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VOPInstructions.td
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[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
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2021-06-16 13:36:02 +01:00 |
