Andrea Di Biagio d69af04f28 Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555. ... The reason why build #25777 might have failed is because the SmallVector move constructor is _not_ noexcept, and the stl implementation used by that buildbot calls _VSTD::move_if_noexcept() (according to the backtrace). OpcodeInfo has a default move constructor, and the copy constructor is deleted. However, as far as I can see, SmallVector doesn't declare a noexcept move constructor. So, what I believe it is happening here is that, _VSTD::move_if_noexcept() returns an lvalue reference and not an rvalue reference. This eventually triggers a copy that fails to compile. Hopefully, using a std::vector instead of SmallVector (as it was originally suggested by Simon in the code review) should be enough to unbreak the buildbot. llvm-svn: 342561		2018-09-19 17:54:01 +00:00
..
AsmMatcherEmitter.cpp	[Tablegen] Optimize isSubsetOf() in AsmMatcherEmitter.cpp. NFC	2018-07-13 16:36:14 +00:00
AsmWriterEmitter.cpp	[TableGen] Prevent double flattening of InstAlias asm strings in the asm matcher emitter.	2018-06-18 01:28:01 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
Attributes.cpp
CallingConvEmitter.cpp
CMakeLists.txt	[WebAssembly] TableGen backend for stackifying instructions	2018-08-27 22:02:09 +00:00
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp	[TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::set() where possible. NFCI.	2018-09-19 12:23:50 +00:00
CodeGenDAGPatterns.h	[TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode	2018-08-17 15:54:07 +00:00
CodeGenHwModes.cpp
CodeGenHwModes.h
CodeGenInstruction.cpp	[WebAssembly] Add isEHScopeReturn instruction property	2018-08-21 19:44:11 +00:00
CodeGenInstruction.h	[WebAssembly] Add isEHScopeReturn instruction property	2018-08-21 19:44:11 +00:00
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp	[X86] Add phony registers for high halves of regs with low halves	2018-07-02 19:05:09 +00:00
CodeGenRegisters.h	[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum	2018-08-16 15:29:24 +00:00
CodeGenSchedule.cpp	[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.	2018-09-19 15:57:45 +00:00
CodeGenSchedule.h	Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555.	2018-09-19 17:54:01 +00:00
CodeGenTarget.cpp	[GlobalISel][Tablegen] Assign small opcodes to pseudos	2018-05-23 22:10:21 +00:00
CodeGenTarget.h	[GlobalISel][Tablegen] Assign small opcodes to pseudos	2018-05-23 22:10:21 +00:00
CTagsEmitter.cpp
DAGISelEmitter.cpp	[TableGen] Support multi-alternative pattern fragments	2018-07-13 13:18:00 +00:00
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp	[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum	2018-08-16 15:29:24 +00:00
DAGISelMatcherOpt.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
DFAPacketizerEmitter.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
DisassemblerEmitter.cpp	[WebAssembly] Initial Disassembler.	2018-05-10 22:16:44 +00:00
FastISelEmitter.cpp	[TableGen] Use std::move where possible in InstructionMemo constructor. NFCI.	2018-08-28 11:10:27 +00:00
FixedLenDecoderEmitter.cpp	[windows] Don't inline fieldFromInstruction on Windows	2018-07-25 17:33:20 +00:00
GlobalISelEmitter.cpp	[globalisel] Remove dead code from GlobalISelEmitter	2018-08-12 21:49:42 +00:00
InfoByHwMode.cpp
InfoByHwMode.h	[TableGen] Don't separately search for DefaultMode when we're going to iterate the set anyway. NFCI.	2018-08-17 17:45:15 +00:00
InstrDocsEmitter.cpp	[WebAssembly] Add isEHScopeReturn instruction property	2018-08-21 19:44:11 +00:00
InstrInfoEmitter.cpp	[WebAssembly] Add isEHScopeReturn instruction property	2018-08-21 19:44:11 +00:00
IntrinsicEmitter.cpp	[Power9] Add __float128 builtins for Round To Odd	2018-07-09 18:50:06 +00:00
LLVMBuild.txt
OptParserEmitter.cpp
PredicateExpander.cpp	[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.	2018-09-19 15:57:45 +00:00
PredicateExpander.h	[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.	2018-09-19 15:57:45 +00:00
PseudoLoweringEmitter.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
RegisterBankEmitter.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
RegisterInfoEmitter.cpp	[MC] Remove PhysRegSize from MCRegisterClass	2018-08-09 15:19:07 +00:00
RISCVCompressInstEmitter.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
SDNodeProperties.cpp
SDNodeProperties.h
SearchableTableEmitter.cpp	TableGen/SearchableTables: Cast enums to unsigned in generated code	2018-08-23 08:02:02 +00:00
SequenceToOffsetTable.h
SubtargetEmitter.cpp	[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.	2018-09-19 15:57:45 +00:00
SubtargetFeatureInfo.cpp
SubtargetFeatureInfo.h
TableGen.cpp	[WebAssembly] TableGen backend for stackifying instructions	2018-08-27 22:02:09 +00:00
TableGenBackends.h	[WebAssembly] TableGen backend for stackifying instructions	2018-08-27 22:02:09 +00:00
tdtags
Types.cpp
Types.h
WebAssemblyDisassemblerEmitter.cpp	[WebAssembly] Made disassembler only use stack instructions.	2018-08-30 15:40:53 +00:00
WebAssemblyDisassemblerEmitter.h	[WebAssembly] Initial Disassembler.	2018-05-10 22:16:44 +00:00
WebAssemblyStackifierEmitter.cpp	[WebAssembly][NFC] Document stackifier tablegen backend	2018-08-28 18:49:47 +00:00
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86EVEX2VEXTablesEmitter.cpp	[X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter.	2018-06-19 04:24:44 +00:00
X86FoldTablesEmitter.cpp	[X86] More additions to the load folding tables based on the autogenerated tables.	2018-06-16 23:25:50 +00:00
X86ModRMFilters.cpp
X86ModRMFilters.h	Test commit: remove trailing whitespace	2018-09-11 17:28:43 +00:00
X86RecognizableInstr.cpp	[X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.	2018-08-13 22:06:28 +00:00
X86RecognizableInstr.h	[X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0.	2018-06-19 04:24:42 +00:00