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This patch adds the ability for processor models to describe dependency breaking
instructions.
Different processors may specify a different set of dependency-breaking
instructions.
That means, we cannot assume that all processors of the same target would use
the same rules to classify dependency breaking instructions.
The main goal of this patch is to provide the means to describe dependency
breaking instructions directly via tablegen, and have the following
TargetSubtargetInfo hooks redefined in overrides by tabegen'd
XXXGenSubtargetInfo classes (here, XXX is a Target name).
```
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
return false;
}
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
return isZeroIdiom(MI);
}
```
An instruction MI is a dependency-breaking instruction if a call to method
isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to
true. Similarly, an instruction MI is a special case of zero-idiom dependency
breaking instruction if a call to STI.isZeroIdiom(MI) returns true.
The extra APInt is used for those targets that may want to select which machine
operands have their dependency broken (see comments in code).
Note that by default, subtargets don't know about the existence of
dependency-breaking. In the absence of external information, those method calls
would always return false.
A new tablegen class named STIPredicate has been added by this patch to let
processor models classify instructions that have properties in common. The idea
is that, a MCInstrPredicate definition can be used to "generate" an instruction
equivalence class, with the idea that instructions of a same class all have a
property in common.
STIPredicate definitions are essentially a collection of instruction equivalence
classes.
Also, different processor models can specify a different variant of the same
STIPredicate with different rules (i.e. predicates) to classify instructions.
Tablegen backends (in this particular case, the SubtargetEmitter) will be able
to process STIPredicate definitions, and automatically generate functions in
XXXGenSubtargetInfo.
This patch introduces two special kind of STIPredicate classes named
IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a
definition for those in the BtVer2 scheduling model only.
This patch supersedes the one committed at r338372 (phabricator review: D49310).
The main advantages are:
- We can describe subtarget predicates via tablegen using STIPredicates.
- We can describe zero-idioms / dep-breaking instructions directly via
tablegen in the scheduling models.
In future, the STIPredicates framework can be used for solving other problems.
Examples of future developments are:
- Teach how to identify optimizable register-register moves
- Teach how to identify slow LEA instructions (each subtarget defining its own
concept of "slow" LEA).
- Teach how to identify instructions that have undocumented false dependencies
on the output registers on some processors only.
It is also (in my opinion) an elegant way to expose knowledge to both external
tools like llvm-mca, and codegen passes.
For example, machine schedulers in LLVM could reuse that information when
internally constructing the data dependency graph for a code region.
This new design feature is also an "opt-in" feature. Processor models don't have
to use the new STIPredicates. It has all been designed to be as unintrusive as
possible.
Differential Revision: https://reviews.llvm.org/D52174
llvm-svn: 342555
118 lines
4.8 KiB
C++
118 lines
4.8 KiB
C++
//===--------------------- PredicateExpander.h ----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// Functionalities used by the Tablegen backends to expand machine predicates.
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///
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/// See file llvm/Target/TargetInstrPredicate.td for a full list and description
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/// of all the supported MCInstPredicate classes.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UTILS_TABLEGEN_PREDICATEEXPANDER_H
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#define LLVM_UTILS_TABLEGEN_PREDICATEEXPANDER_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Record.h"
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namespace llvm {
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class raw_ostream;
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class PredicateExpander {
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bool EmitCallsByRef;
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bool NegatePredicate;
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bool ExpandForMC;
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unsigned IndentLevel;
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StringRef TargetName;
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PredicateExpander(const PredicateExpander &) = delete;
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PredicateExpander &operator=(const PredicateExpander &) = delete;
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public:
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PredicateExpander(StringRef Target)
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: EmitCallsByRef(true), NegatePredicate(false), ExpandForMC(false),
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IndentLevel(1U), TargetName(Target) {}
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bool isByRef() const { return EmitCallsByRef; }
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bool shouldNegate() const { return NegatePredicate; }
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bool shouldExpandForMC() const { return ExpandForMC; }
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unsigned getIndentLevel() const { return IndentLevel; }
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StringRef getTargetName() const { return TargetName; }
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void setByRef(bool Value) { EmitCallsByRef = Value; }
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void flipNegatePredicate() { NegatePredicate = !NegatePredicate; }
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void setNegatePredicate(bool Value) { NegatePredicate = Value; }
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void setExpandForMC(bool Value) { ExpandForMC = Value; }
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void setIndentLevel(unsigned Level) { IndentLevel = Level; }
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void increaseIndentLevel() { ++IndentLevel; }
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void decreaseIndentLevel() { --IndentLevel; }
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using RecVec = std::vector<Record *>;
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void expandTrue(raw_ostream &OS);
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void expandFalse(raw_ostream &OS);
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void expandCheckImmOperand(raw_ostream &OS, int OpIndex, int ImmVal);
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void expandCheckImmOperand(raw_ostream &OS, int OpIndex, StringRef ImmVal);
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void expandCheckRegOperand(raw_ostream &OS, int OpIndex, const Record *Reg);
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void expandCheckSameRegOperand(raw_ostream &OS, int First, int Second);
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void expandCheckNumOperands(raw_ostream &OS, int NumOps);
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void expandCheckOpcode(raw_ostream &OS, const Record *Inst);
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void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
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void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
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void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
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bool IsCheckAll);
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void expandTIIFunctionCall(raw_ostream &OS, StringRef MethodName);
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void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
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void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
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void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
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void expandCheckFunctionPredicate(raw_ostream &OS, StringRef MCInstFn,
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StringRef MachineInstrFn);
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void expandCheckNonPortable(raw_ostream &OS, StringRef CodeBlock);
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void expandPredicate(raw_ostream &OS, const Record *Rec);
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void expandReturnStatement(raw_ostream &OS, const Record *Rec);
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void expandOpcodeSwitchCase(raw_ostream &OS, const Record *Rec);
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void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
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const Record *Default);
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void expandStatement(raw_ostream &OS, const Record *Rec);
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};
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// Forward declarations.
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class STIPredicateFunction;
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class OpcodeGroup;
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class STIPredicateExpander : public PredicateExpander {
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StringRef ClassPrefix;
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bool ExpandDefinition;
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STIPredicateExpander(const PredicateExpander &) = delete;
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STIPredicateExpander &operator=(const PredicateExpander &) = delete;
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void expandHeader(raw_ostream &OS, const STIPredicateFunction &Fn);
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void expandPrologue(raw_ostream &OS, const STIPredicateFunction &Fn);
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void expandOpcodeGroup(raw_ostream &OS, const OpcodeGroup &Group,
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bool ShouldUpdateOpcodeMask);
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void expandBody(raw_ostream &OS, const STIPredicateFunction &Fn);
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void expandEpilogue(raw_ostream &OS, const STIPredicateFunction &Fn);
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public:
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STIPredicateExpander(StringRef Target)
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: PredicateExpander(Target), ClassPrefix(), ExpandDefinition(false) {}
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bool shouldExpandDefinition() const { return ExpandDefinition; }
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StringRef getClassPrefix() const { return ClassPrefix; }
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void setClassPrefix(StringRef S) { ClassPrefix = S; }
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void setExpandDefinition(bool Value) { ExpandDefinition = Value; }
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void expandSTIPredicate(raw_ostream &OS, const STIPredicateFunction &Fn);
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};
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} // namespace llvm
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#endif
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