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f3da7ee9fe
Summary: In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the `PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch should resolve PR45297. Differential Revision: https://reviews.llvm.org/D76773
23 lines
755 B
LLVM
23 lines
755 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
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; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
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@Global = dso_local global i32 55, align 4
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define dso_local void @test(float %0) local_unnamed_addr {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fctiwz f0, f1
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; CHECK-NEXT: addi r3, r1, -4
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; CHECK-NEXT: addis r4, r2, Global@toc@ha
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: lwz r3, -4(r1)
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; CHECK-NEXT: stw r3, Global@toc@l(r4)
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; CHECK-NEXT: blr
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entry:
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%1 = fptosi float %0 to i32
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store i32 %1, i32* @Global, align 4
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ret void
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}
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