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e3e2fa9c0a
Summary: For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files. For more obvious cases, I've ventured a fix. Some notes: - Exynos is especially fishy. - AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice. - The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit. Also see PR37310. Reviewers: RKSimon, craig.topper, javed.absar Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46356 llvm-svn: 334586 |
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| .. | ||
| GlobalISel | ||
| CodeGenCWrappers.h | ||
| GenericOpcodes.td | ||
| Target.td | ||
| TargetCallingConv.td | ||
| TargetInstrPredicate.td | ||
| TargetIntrinsicInfo.h | ||
| TargetItinerary.td | ||
| TargetLoweringObjectFile.h | ||
| TargetMachine.h | ||
| TargetOptions.h | ||
| TargetSchedule.td | ||
| TargetSelectionDAG.td | ||