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llvm-mirror/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
Matt Arsenault c1329a6c94 AMDGPU: Relax 32-bit SGPR register class
Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This
will allow the register coalescer to do a better job eliminating
copies to m0.

For GlobalISel, as a terrible hack, use SGPR_32 for things that should
use SCC until booleans are solved.

llvm-svn: 375267
2019-10-18 18:26:37 +00:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN
---
name: frame_index_s
legalized: true
regBankSelected: true
stack:
- { id: 0, size: 4, alignment: 4 }
body: |
bb.0:
; GCN-LABEL: name: frame_index_s
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 %stack.0
; GCN: $sgpr0 = COPY [[S_MOV_B32_]]
%0:sgpr(p5) = G_FRAME_INDEX %stack.0
$sgpr0 = COPY %0
...
---
name: frame_index_v
legalized: true
regBankSelected: true
stack:
- { id: 0, size: 4, alignment: 4 }
body: |
bb.0:
; GCN-LABEL: name: frame_index_v
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GCN: $vgpr0 = COPY [[V_MOV_B32_e32_]]
%0:vgpr(p5) = G_FRAME_INDEX %stack.0
$vgpr0 = COPY %0
...