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31a388b7dd
AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
207 lines
6.8 KiB
YAML
207 lines
6.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: ctpop_s32_s32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ctpop_s32_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
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; CHECK: $vgpr0 = COPY [[CTPOP]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CTPOP %0
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$vgpr0 = COPY %1
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...
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---
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name: ctpop_s32_s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: ctpop_s32_s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s64)
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; CHECK: $vgpr0 = COPY [[CTPOP]](s32)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CTPOP %0
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$vgpr0 = COPY %1
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...
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---
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name: ctpop_s64_s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: ctpop_s64_s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s64)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_CTPOP %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: ctpop_s16_s32
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ctpop_s16_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_CTPOP %0
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%2:_(s32) = G_ZEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: ctpop_s16_s16
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ctpop_s16_s16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s16) = G_CTPOP %1
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%3:_(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: ctpop_v2s32_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: ctpop_v2s32_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[UV]](s32)
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; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[UV1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTPOP]](s32), [[CTPOP1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = G_CTPOP %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: ctpop_v2s32_v2s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: ctpop_v2s32_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[UV]](s64)
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; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[UV1]](s64)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTPOP]](s32), [[CTPOP1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<2 x s32>) = G_CTPOP %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: ctpop_v2s16_v2s16
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ctpop_v2s16_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
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; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTPOP1]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
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; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s16>) = G_CTPOP %0
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$vgpr0 = COPY %1
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...
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---
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name: ctpop_s7_s7
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ctpop_s7_s7
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s7) = G_TRUNC %0
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%2:_(s7) = G_CTPOP %1
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%3:_(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: ctpop_s33_s33
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: ctpop_s33_s33
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
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; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s64)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
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; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
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; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s33) = G_TRUNC %0
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%2:_(s33) = G_CTPOP %1
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%3:_(s64) = G_ANYEXT %2
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$vgpr0_vgpr1 = COPY %3
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...
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