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430af4239a
The usage of target boolean checks is overly inflexible, since sext and zext of a compare are equally cheap. The choice is arbitrary, but using 0/1 to some degree is the choice of lower resistance since that's what most targets use. This enables a few combines that don't bother to support ZeroOrNegativeOneBooleanContent.
26 lines
992 B
LLVM
26 lines
992 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @test_wave64(i32 %arg0, [8 x i32], i64 %saved) {
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; GCN-LABEL: test_wave64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s2, s[4:5], 0x0
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_eq_u32 s2, 0
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; GCN-NEXT: s_cselect_b32 s2, 1, 0
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; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
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; GCN-NEXT: s_endpgm
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entry:
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%cond = icmp eq i32 %arg0, 0
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%break = call i64 @llvm.amdgcn.if.break.i64(i1 %cond, i64 %saved)
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store volatile i64 %break, i64 addrspace(1)* undef
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ret void
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}
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declare i64 @llvm.amdgcn.if.break.i64(i1, i64)
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