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llvm-mirror/test/CodeGen/AArch64/scheduledag-constreg.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts
--- |
define void @func() { ret void }
...
---
# Check that the instructions are not dependent on each other, even though
# they all read/write to the zero register.
# CHECK-LABEL: MI Scheduling
# CHECK: SU(0): dead $wzr = SUBSWri $w1, 0, 0, implicit-def dead $nzcv
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(1): $w2 = COPY $wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(2): dead $wzr = SUBSWri $w3, 0, 0, implicit-def dead $nzcv
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(3): $w4 = COPY $wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
name: func
body: |
bb.0:
dead $wzr = SUBSWri $w1, 0, 0, implicit-def dead $nzcv
$w2 = COPY $wzr
dead $wzr = SUBSWri $w3, 0, 0, implicit-def dead $nzcv
$w4 = COPY $wzr
...