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61ff754920
This adds the plumbing for the Tiny code model for the AArch64 backend. This, instead of loading addresses through the normal ADRP;ADD pair used in the Small model, uses a single ADR. The 21 bit range of an ADR means that the code and its statically defined symbols need to be within 1MB of each other. This makes it mostly interesting for embedded applications where we want to fit as much as we can in as small a space as possible. Differential Revision: https://reviews.llvm.org/D49673 llvm-svn: 340397
34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s
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; RUN: llc -code-model=tiny -mtriple=aarch64-none-none-eabi -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-TINY %s
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@addr = global i8* null
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define void @test_blockaddress() {
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; CHECK-LABEL: test_blockaddress:
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store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
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%val = load volatile i8*, i8** @addr
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indirectbr i8* %val, [label %block]
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; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]]
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; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]]
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; CHECK: str [[DEST]],
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; CHECK: ldr [[NEWDEST:x[0-9]+]]
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; CHECK: br [[NEWDEST]]
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; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
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; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
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; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
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; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
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; CHECK-LARGE: str [[ADDR_REG]],
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; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]]
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; CHECK-LARGE: br [[NEWDEST]]
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; CHECK-TINY: adr [[DEST:x[0-9]+]], {{.Ltmp[0-9]+}}
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; CHECK-TINY: str [[DEST]],
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; CHECK-TINY: ldr [[NEWDEST:x[0-9]+]]
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; CHECK-TINY: br [[NEWDEST]]
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block:
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ret void
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}
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