Dmitry Preobrazhensky 09506da3e3 [AMDGPU][MC] Corrected parsing of registers ... Summary of changes: refactored code for better readability and future improvements; fixed bug 41281: https://bugs.llvm.org/show_bug.cgi?id=41281 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D65224 llvm-svn: 373094		2019-09-27 15:41:31 +00:00
..
AArch64	AArch64: support arm64_32, an ILP32 slice for watchOS.	2019-09-12 10:22:23 +00:00
AMDGPU	[AMDGPU][MC] Corrected parsing of registers	2019-09-27 15:41:31 +00:00
ARM	[MC][ARM] vscclrm disassembles as vldmia	2019-09-27 08:22:24 +00:00
AsmParser	Remove some unnecessary REQUIRES: shell lines	2019-09-10 00:06:52 +00:00
AVR
BPF
COFF	[X86] Print register names in .seh_* directives	2019-08-30 21:23:05 +00:00
Disassembler	[MC][ARM] vscclrm disassembles as vldmia	2019-09-27 08:22:24 +00:00
ELF	Remove some unnecessary REQUIRES: shell lines	2019-09-10 00:06:52 +00:00
Hexagon
Lanai
MachO	[MachO][TLOF] Use hasLocalLinkage to determine if indirect symbol is local	2019-08-22 16:59:00 +00:00
Mips	[mips] Expand 'lw/sw' instructions for 32-bit GOT	2019-09-18 19:19:47 +00:00
MSP430
PowerPC	[PowerPC] Support extended mnemonics mffprwz etc.	2019-08-29 21:53:59 +00:00
RISCV	[RISCV] Support llvm-objdump -M no-aliases and -M numeric	2019-09-10 16:24:03 +00:00
Sparc
SystemZ	[SystemZ] Support z15 processor name	2019-09-20 23:04:45 +00:00
WebAssembly	[WebAssembly] v128.andnot	2019-09-27 02:11:40 +00:00
X86	[MC] Pass through .code16/32/64 and .syntax unified for COFF	2019-09-03 18:16:52 +00:00