Quentin Colombet dbdfe6759b [R600] Replicate old DAGCombiner behavior in target specific DAG combine. ... build_vector is lowered to REG_SEQUENCE, which is something the register allocator does a good job at optimizing. llvm-svn: 187397		2013-07-30 00:27:16 +00:00
..
AArch64	AArch64: add llc-based tests for previous commit.	2013-07-25 16:23:55 +00:00
ARM	[DAGCombiner] insert_vector_elt: Avoid building a vector twice.	2013-07-30 00:24:09 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Inputs	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Mips	[mips] Implement llvm.trap intrinsic.	2013-07-26 20:58:55 +00:00
MSP430	Use conventional syntax for branches.	2013-07-14 18:19:44 +00:00
NVPTX	Add a target legalize hook for SplitVectorOperand (again)	2013-07-26 13:28:29 +00:00
PowerPC	PPC32 va_list is an actual structure so va_copy needs to copy the whole	2013-07-25 21:36:47 +00:00
R600	[R600] Replicate old DAGCombiner behavior in target specific DAG combine.	2013-07-30 00:27:16 +00:00
SI
SPARC	Allocate local registers in order for optimal coloring.	2013-07-25 18:35:14 +00:00
SystemZ	[SystemZ] Rework compare and branch support	2013-07-25 09:34:38 +00:00
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2	Refactor AnalyzeBranch on ARM. The previous version did not always analyze	2013-07-19 23:52:47 +00:00
X86	[DAGCombiner] insert_vector_elt: Avoid building a vector twice.	2013-07-30 00:24:09 +00:00
XCore	Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change.	2013-07-18 22:29:15 +00:00