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7e501cf4c3
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
llvm-svn: 186280
118 lines
2.5 KiB
LLVM
118 lines
2.5 KiB
LLVM
; Test 32-bit comparisons in which the second operand is a PC-relative
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; variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i32 1
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@h = global i32 1, align 2, section "foo"
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; Check signed comparisons.
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define i32 @f1(i32 %src1) {
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; CHECK-LABEL: f1:
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; CHECK: crl %r2, g
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@g
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%cond = icmp slt i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Check unsigned comparisons.
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define i32 @f2(i32 %src1) {
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; CHECK-LABEL: f2:
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; CHECK: clrl %r2, g
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@g
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Check equality, which can use CRL or CLRL.
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define i32 @f3(i32 %src1) {
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; CHECK-LABEL: f3:
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; CHECK: c{{l?}}rl %r2, g
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; CHECK-NEXT: je
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@g
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%cond = icmp eq i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; ...likewise inequality.
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define i32 @f4(i32 %src1) {
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; CHECK-LABEL: f4:
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; CHECK: c{{l?}}rl %r2, g
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; CHECK-NEXT: jlh
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@g
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%cond = icmp ne i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f1 with an unaligned address.
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define i32 @f5(i32 %src1) {
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; CHECK-LABEL: f5:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: c %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@h, align 2
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%cond = icmp slt i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f2 with an unaligned address.
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define i32 @f6(i32 %src1) {
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; CHECK-LABEL: f6:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: cl %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@h, align 2
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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