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https://github.com/RPCS3/llvm-mirror.git
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59de807f62
This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
335 lines
9.6 KiB
YAML
335 lines
9.6 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: hazard_smem_war
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# GCN: S_LOAD_DWORD_IMM
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_no_hazard
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_ADD_U32
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_no_hazard
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$sgpr3 = S_ADD_U32 $sgpr4, $sgpr5, implicit-def $scc
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_dependent_salu
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT
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# GCN-NEXT: S_ADD_U32
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_dependent_salu
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 0
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$sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_independent_salu
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT
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# GCN-NEXT: S_ADD_U32
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_independent_salu
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 0
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$sgpr3 = S_ADD_U32 $sgpr5, $sgpr4, implicit-def $scc
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_smem
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_LOAD_DWORD_IMM
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# GCN-NEXT: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_smem
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr6, $sgpr7, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$sgpr5 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0, 0
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_waitcnt_0
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_waitcnt_0
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 0
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_vmcnt_0
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT 3952{{$}}
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# GCN-NEXT: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_vmcnt_0
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 3952
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_expcnt_0
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT 53007{{$}}
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# GCN-NEXT: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_expcnt_0
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 53007
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_lgkmcnt_0
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT 49279{{$}}
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_lgkmcnt_0
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT 49279
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_0
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT_LGKMCNT
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_waitcnt_lgkmcnt_0
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT_LGKMCNT $sgpr_null, 0
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_1
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# GCN: S_LOAD_DWORD_IMM
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# GCN-NEXT: S_WAITCNT_LGKMCNT
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# GCN-NEXT: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_only_waitcnt_lgkmcnt_1
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_WAITCNT_LGKMCNT $sgpr_null, 1
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_branch
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# GCN: S_LOAD_DWORD_IMM
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_branch
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
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successors: %bb.1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_BRANCH %bb.1
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bb.1:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_cbranch
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# GCN: S_AND_B64
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# GCN: S_LOAD_DWORD_IMM
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# GCN: S_CBRANCH_VCCZ
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# GCN-NOT: $sgpr_null = S_MOV_B32 0
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# GCN: V_CMP_EQ_F32
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# GCN: S_ENDPGM 0
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_cbranch
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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successors: %bb.1, %bb.2
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$vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
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bb.1:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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bb.2:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_cbranch_carry
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# GCN: S_AND_B64
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# GCN: S_LOAD_DWORD_IMM
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# GCN: S_CBRANCH_VCCZ
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# GCN-NOT: $sgpr_null = S_MOV_B32 0
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# GCN: V_CMP_EQ_F32
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# GCN-NEXT: S_ENDPGM 0
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# GCN-NOT: $sgpr_null = S_MOV_B32 0
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# GCN: V_CMP_EQ_F32
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_cbranch_carry
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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successors: %bb.1, %bb.2
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$vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
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bb.1:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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bb.2:
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successors: %bb.3
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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bb.3:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_backedge
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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# GCN: S_LOAD_DWORD_IMM
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---
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name: hazard_smem_war_backedge
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
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successors: %bb.1
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$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
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bb.1:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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S_BRANCH %bb.0
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...
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# GCN-LABEL: name: hazard_smem_war_impdef
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# GCN: S_LOAD_DWORD_IMM
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_CMP_EQ_F32
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---
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name: hazard_smem_war_impdef
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body: |
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bb.0:
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liveins: $vcc, $vgpr0
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$sgpr0 = S_LOAD_DWORD_IMM $vcc, 0, 0, 0
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V_CMP_EQ_F32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_readlane
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# GCN: S_LOAD_DWORD_IMM
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_READLANE_B32
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---
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name: hazard_smem_war_readlane
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$sgpr0 = V_READLANE_B32 $vgpr0, $sgpr3
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S_ENDPGM 0
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...
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# Workaround since spilling/restoring SGPRs use real opcodes.
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# GCN-LABEL: name: hazard_smem_war_readlane_gfx10
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# GCN: S_LOAD_DWORD_IMM
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_READLANE_B32_gfx10
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---
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name: hazard_smem_war_readlane_gfx10
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3
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S_ENDPGM 0
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...
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# GCN-LABEL: name: hazard_smem_war_readfirstlane
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# GCN: S_LOAD_DWORD_IMM
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# GCN: $sgpr_null = S_MOV_B32 0
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# GCN-NEXT: V_READFIRSTLANE_B32
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---
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name: hazard_smem_war_readfirstlane
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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$sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
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S_ENDPGM 0
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...
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