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llvm-mirror/test/CodeGen/AMDGPU
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Matt Arsenault dd82110acb AMDGPU: Remove SIFixupVectorISel pass 
This was only used for matching the saddr addressing mode of global
instructions, but this was not implemented correctly. The instruction
definitions aren't even correct, and are defined as using a 64-bit
VGPR component. Eliminate this pass to enable correcting the
instruction definitions. A new matching implementation can work in
GlobalISel or relying on DAG divergence information for the base
address.
2020-08-15 12:11:51 -04:00
..
GlobalISel
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV
2020-08-14 13:55:30 -04:00
32-bit-local-address-space.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
aa-points-to-constant-memory.ll
AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory
2020-05-09 16:00:08 -04:00
accvgpr-copy.mir
AMDGPU: Fix liveness errors when copying AGPR tuples
2020-07-30 18:13:04 -04:00
add3.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
add_i1.ll
…
add_i64.ll
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add_i128.ll
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add_shl.ll
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add-debug.ll
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add.i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
add.ll
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add.v2i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
addrspacecast-captured.ll
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addrspacecast-constantexpr.ll
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addrspacecast-initializer-unsupported.ll
Support addrspacecast initializers with isNoopAddrSpaceCast
2020-07-31 10:42:43 -04:00
addrspacecast-initializer.ll
Support addrspacecast initializers with isNoopAddrSpaceCast
2020-07-31 10:42:43 -04:00
addrspacecast.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
adjust-writemask-invalid-copy.ll
…
agpr-register-count.ll
…
agpr-remat.ll
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
alignbit-pat.ll
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alloca.ll
AllocaInst should store Align instead of MaybeAlign.
2020-05-16 14:53:16 -07:00
always-uniform.ll
…
amdgcn-ieee.ll
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
amdgcn-load-offset-from-reg.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
amdgcn.bitcast.ll
[AMDGPU] Fix crash when dag-combining bitcast
2020-08-13 10:23:13 +08:00
amdgcn.private-memory.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
amdgpu-alias-analysis.ll
[BasicAA] Rename -disable-basicaa to -disable-basic-aa to be consistent with the canonical name "basic-aa"
2020-06-26 20:55:44 -07:00
amdgpu-codegenprepare-fdiv.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
amdgpu-codegenprepare-fold-binop-select.ll
[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
2020-07-08 19:14:48 +01:00
amdgpu-codegenprepare-i16-to-i32.ll
AMDGPU: Generate test checks
2020-01-20 20:03:45 -05:00
amdgpu-codegenprepare-idiv.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
amdgpu-codegenprepare-mul24.ll
…
amdgpu-function-calls-option.ll
…
amdgpu-inline.ll
[AMDGPU] Tune inlining parameters for AMDGPU target (part 2)
2019-11-19 16:33:16 +03:00
amdgpu-mul24-knownbits.ll
[AMDGPU] simplifyI24 - replace GetDemandedBits with SimplifyMultipleUseDemandedBits
2020-02-20 12:03:08 +00:00
amdgpu-reloc-const.ll
AMDGPU/GlobalISel: Handle llvm.amdgcn.reloc.constant
2020-07-29 14:24:21 -04:00
amdgpu-shader-calling-convention.ll
…
amdgpu-unroll-threshold.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
amdgpu.private-memory.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
amdgpu.work-item-intrinsics.deprecated.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
amdhsa-trap-num-sgprs.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
amdpal_scratch_mergedshader.ll
…
amdpal-cs.ll
…
amdpal-elf.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
amdpal-es.ll
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amdpal-gs.ll
…
amdpal-hs.ll
…
amdpal-ls.ll
…
amdpal-msgpack-cs.ll
…
amdpal-msgpack-es.ll
…
amdpal-msgpack-gs.ll
…
amdpal-msgpack-hs.ll
…
amdpal-msgpack-ls.ll
…
amdpal-msgpack-ps.ll
…
amdpal-msgpack-psenable.ll
…
amdpal-msgpack-vs.ll
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amdpal-ps.ll
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amdpal-psenable.ll
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amdpal-vs.ll
…
amdpal.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
and_or.ll
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and-gcn.ll
…
and.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
andorbitset.ll
AMDGPU: Fix verifier error with undef source producing s_bitset*
2020-08-05 14:42:20 -04:00
andorn2.ll
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andorxorinvimm.ll
…
annotate-kernel-features-hsa-call.ll
AMDGPU: Add IntrWillReturn to intrinsic definitions
2020-06-18 15:38:10 -04:00
annotate-kernel-features-hsa.ll
AMDGPU: Add IntrWillReturn to intrinsic definitions
2020-06-18 15:38:10 -04:00
annotate-kernel-features.ll
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anonymous-gv.ll
…
any_extend_vector_inreg.ll
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anyext.ll
…
are-loads-from-same-base-ptr.ll
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array-ptr-calc-i32.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
array-ptr-calc-i64.ll
…
ashr.v2i16.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
asm-printer-check-vcc.mir
[amdgpu] Fix check of VCC.
2020-05-06 14:16:37 -04:00
at-least-one-def-value-assert.mir
[AMDGPU] Define 16 bit VGPR subregs
2020-03-31 11:49:06 -07:00
atomic_cmp_swap_local.ll
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atomic_load_add.ll
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atomic_load_local.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
atomic_load_sub.ll
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atomic_optimizations_buffer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_optimizations_global_pointer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] New llvm.amdgcn.ballot intrinsic
2020-03-31 10:35:39 +02:00
atomic_store_local.ll
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atomicrmw-nand.ll
…
attr-amdgpu-flat-work-group-size-v3.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[AMDGPU] Fix getEUsPerCU for gfx10 in CU mode
2020-03-27 20:36:49 +00:00
attr-amdgpu-flat-work-group-size.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
attr-amdgpu-num-sgpr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
attr-amdgpu-num-vgpr.ll
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attr-amdgpu-waves-per-eu.ll
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attr-unparseable.ll
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barrier-elimination.ll
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basic-branch.ll
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basic-call-return.ll
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basic-loop.ll
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bfe_uint.ll
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bfe-combine.ll
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bfe-patterns.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
bfi_int.ll
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bfm.ll
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big_alu.ll
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bitcast-constant-to-vector.ll
[MachineScheduler] Reduce reordering due to mem op clustering
2020-01-14 19:19:02 +00:00
bitcast-v4f16-v4i16.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
bitcast-vector-extract.ll
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bitreverse-inline-immediates.ll
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bitreverse.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
br_cc.f16.ll
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branch-condition-and.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
branch-relax-bundle.ll
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branch-relax-spill.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
branch-relaxation-debug-info.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
branch-relaxation-inst-size-gfx10.ll
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branch-relaxation.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
branch-uniformity.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
break-smem-soft-clauses.mir
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break-vmem-soft-clauses.mir
[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer
2020-05-05 15:49:09 +01:00
bswap.ll
[DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG
2020-07-29 18:10:59 +01:00
buffer-intrinsics-mmo-offsets.ll
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
buffer-schedule.ll
…
bug-sdag-scheduler-cycle.ll
SelectionDAG: Fix bug in ClusterNeighboringLoads
2020-02-12 09:12:55 +01:00
bug-vopc-commute.ll
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build_vector.ll
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build-vector-insert-elt-infloop.ll
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build-vector-packed-partial-undef.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
bundle-latency.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
bypass-div.ll
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
byval-frame-setup.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
call_fs.ll
…
call-argument-types.ll
[Scheduling] Create the missing dependency edges for store cluster
2020-08-07 04:58:03 +00:00
call-constant.ll
AMDGPU: Don't assume call targets are registers
2020-07-28 20:46:06 -04:00
call-constexpr.ll
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call-encoding.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
call-graph-register-usage.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-preserved-registers.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-return-types.ll
…
call-skip.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
call-to-kernel-undefined.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
call-to-kernel.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
call-waitcnt.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
call-waw-waitcnt.mir
AMDGPU: Avoid overwriting saved PC
2019-10-28 10:02:22 -07:00
callee-frame-setup.ll
[AMDGPU] Fix FP/BP spills when MUBUF constant offset exceeded
2020-08-13 14:12:00 -07:00
callee-special-input-sgprs-fixed-abi.ll
AMDGPU: Fix DAG divergence for implicit function arguments
2020-05-19 18:11:34 -04:00
callee-special-input-sgprs.ll
AMDGPU: Fix DAG divergence for implicit function arguments
2020-05-19 18:11:34 -04:00
callee-special-input-vgprs.ll
[Scheduling] Create the missing dependency edges for store cluster
2020-08-07 04:58:03 +00:00
calling-conventions.ll
AMDGPU: Allow i16 shader arguments
2020-01-27 06:55:32 -08:00
captured-frame-index.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
carryout-selection.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
cayman-loop-bug.ll
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cc-sgpr-limit.ll
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cc-sgpr-over-limit.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
cc-update.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
cf_end.ll
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cf-loop-on-constant.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
cf-stack-bug.ll
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cgp-addressing-modes-flat.ll
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cgp-addressing-modes-gfx908.ll
AMDGPU: Handle a few missing cases in getAddrModeArguments
2020-07-28 20:22:38 -04:00
cgp-addressing-modes-gfx1030.ll
AMDGPU: Handle a few missing cases in getAddrModeArguments
2020-07-28 20:22:38 -04:00
cgp-addressing-modes.ll
AMDGPU: Handle a few missing cases in getAddrModeArguments
2020-07-28 20:22:38 -04:00
cgp-bitfield-extract.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
chain-hi-to-lo.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
clamp-modifier.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
clamp-omod-special-case.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
clamp.ll
AMDGPU: Remove fp-exceptions feature
2020-05-29 15:19:59 -04:00
cluster_stores.ll
[AMDGPU/MemOpsCluster] Compute width for MIMG instruction class.
2020-06-23 17:32:17 +05:30
cluster-flat-loads-postra.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
cluster-flat-loads.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
cmp_shrink.mir
[AMDGPU] Avoid using s_cmpk when src0 is not register
2020-07-14 09:05:53 +01:00
cndmask-no-def-vcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
coalescer_distribute.ll
…
coalescer_remat.ll
…
coalescer-extend-pruned-subrange.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
coalescer-identical-values-undef.mir
…
coalescer-subranges-another-copymi-not-live.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer-subranges-another-prune-error.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer-subranges-prune-kill-copy.mir
…
coalescer-subreg-join.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
coalescer-subregjoin-fullcopy.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescer-with-subregs-bad-identical.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
coalescing-subreg-was-undef-but-became-def.mir
[AMDGPU] Add the test from D49097.
2020-05-20 14:34:51 +01:00
coalescing-with-subregs-in-loop-bug.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
code-object-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
codegen-prepare-addrmode-sext.ll
…
collapse-endcf2.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
collapse-endcf-broken.mir
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collapse-endcf.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
collapse-endcf.mir
[AMDGPU] Limit endcf-collapase to simple if
2020-04-07 10:27:23 -07:00
combine_vloads.ll
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combine-and-sext-bool.ll
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combine-cond-add-sub.ll
Revert "AMDGPU: Try to commute sub of boolean ext"
2019-12-13 12:49:06 +00:00
combine-ftrunc.ll
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comdat.ll
…
commute_modifiers.ll
…
commute-compares.ll
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commute-shifts.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
complex-folding.ll
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computeKnownBits-scalar-to-vector-crash.ll
…
computeNumSignBits-mul.ll
[AMDGPU] Update autogenerated checks
2019-12-17 16:48:02 +00:00
concat_vectors.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
constant-address-space-32bit.ll
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constant-fold-imm-immreg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
constant-fold-mi-operands.ll
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control-flow-fastregalloc.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
control-flow-optnone.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
convergent-inlineasm.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
copy-illegal-type.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
copy-to-reg.ll
…
couldnt-join-subrange-3.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
cross-block-use-is-not-abi-copy.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
cse-phi-incoming-val.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
csr-gfx10.ll
…
ctlz_zero_undef.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
ctlz.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
ctpop16.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
ctpop64.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
ctpop.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
cttz_zero_undef.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
cube.ll
…
cvt_f32_ubyte.ll
[AMDGPU] Regenerate tests to fix whitespace indentations
2020-08-02 18:11:18 +01:00
cvt_flr_i32_f32.ll
…
cvt_rpi_i32_f32.ll
…
dag-divergence.ll
…
dagcomb-shuffle-vecextend-non2.ll
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dagcombine-reassociate-bug.ll
…
dagcombine-select.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
dagcombine-setcc-select.ll
…
dagcombiner-bug-illegal-vec4-int-to-fp.ll
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dce-disjoint-intervals.mir
…
dead_copy.mir
…
dead-lane.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
dead-machine-elim-after-dead-lane.ll
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
2020-01-14 19:26:15 -05:00
debug-value2.ll
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debug-value-scheduler-crash.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
debug-value.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
debug.ll
…
default-fp-mode.ll
AMDGPU: Add some tests for exotic denormal mode combinations
2020-04-02 17:17:12 -04:00
detect-dead-lanes.mir
…
directive-amdgcn-target.ll
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disable_form_clauses.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
disconnected-predset-break-bug.ll
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div_i128.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
diverge-extra-formal-args.ll
…
diverge-interp-mov-lower.ll
…
diverge-switch-default.ll
[InstCombine] fix operands of shouldChangeType() for casted phi transform
2020-02-04 07:45:48 -05:00
divergence-at-use.ll
…
divergent-branch-uniform-condition.ll
[AMDGPU] add generated checks for some LIT tests
2020-03-03 11:47:05 +05:30
divrem24-assume.ll
[AMDGPU] Fix some tests that did not specify -mcpu
2020-02-17 14:02:32 +00:00
dpp_combine.ll
…
dpp_combine.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
drop-mem-operand-move-smrd.ll
…
ds_read2_offset_order.ll
AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets
2020-01-24 19:45:56 -08:00
ds_read2_superreg.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
ds_read2.ll
[llvm] Fix yet more missing FileCheck colons
2020-04-13 10:49:19 -06:00
ds_read2st64.ll
…
ds_write2.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
ds_write2st64.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
ds-combine-large-stride.ll
…
ds-combine-with-dependence.ll
…
ds-negative-offset-addressing-mode-loop.ll
…
ds-sub-offset.ll
…
dynamic_stackalloc.ll
…
early-if-convert-cost.ll
…
early-if-convert.ll
AMDGPU: Fix backwards s_cselect_* operands
2020-05-27 09:26:09 -04:00
early-inline-alias.ll
…
early-inline.ll
…
early-tailduplicator-nophis.mir
TailDuplication: Clear NoPHIs property
2019-12-27 14:06:31 -05:00
elf-header-flags-mach.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
elf-header-flags-sram-ecc.ll
…
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
…
elf-notes.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
elf.ll
[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
2020-03-16 07:42:04 -07:00
elf.metadata.ll
…
elf.r600.ll
[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
2020-03-16 07:42:04 -07:00
else.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
empty-function.ll
…
enable-no-signed-zeros-fp-math.ll
…
endcf-loop-header.ll
…
endpgm-dce.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
enqueue-kernel.ll
…
exceed-max-sgprs.ll
…
expand-scalar-carry-out-select-user.ll
AMDGPU: Don't ignore carry out user when expanding add_co_pseudo
2020-07-06 14:28:01 -04:00
extend-bit-ops-i16.ll
…
extload-align.ll
…
extload-private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
extload.ll
…
extract_subvector_vec4_vec3.ll
Revert "Revert "[MIR] Target specific MIR formating and parsing""
2020-01-08 20:03:29 -08:00
extract_vector_dynelt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
extract_vector_elt-f16.ll
…
extract_vector_elt-f64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extract_vector_elt-i8.ll
…
extract_vector_elt-i16.ll
…
extract_vector_elt-i64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extract-lowbits.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
extract-subvector-equal-length.ll
…
extract-subvector.ll
[AMDGPU] Fixed selection error for 64 bit extract_subvector
2020-05-18 14:17:59 -07:00
extract-vector-elt-build-vector-combine.ll
…
extractelt-to-trunc.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
fabs.f16.ll
…
fabs.f64.ll
…
fabs.ll
…
fadd64.ll
…
fadd-fma-fmul-combine.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
fadd.f16.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
fadd.ll
…
fail-select-buffer-atomic-fadd.ll
AMDGPU: Fix incorrect selection of buffer atomic fadd
2020-06-05 14:34:15 -04:00
fast-unaligned-load-store.global.ll
[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.
2020-05-04 16:42:25 +03:00
fast-unaligned-load-store.private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
fcanonicalize-elimination.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fcanonicalize.f16.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fcanonicalize.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fceil64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
fceil.ll
…
fcmp64.ll
…
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
fcmp.ll
…
fconst64.ll
…
fcopysign.f16.ll
…
fcopysign.f32.ll
…
fcopysign.f64.ll
…
fdiv32-to-rcp-folding.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fdiv-nofpexcept.ll
AMDGPU: Add test for fdiv nofpexcept preservation
2020-06-04 17:35:27 -04:00
fdiv.f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fdiv.f64.ll
…
fdiv.ll
[DAGCombiner] Require ninf for division estimation
2020-06-14 22:58:22 +08:00
fdot2.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fence-barrier.ll
…
fence-lds-read2-write2.ll
AMDGPU: Break read2/write2 search range on a memory fence
2020-04-24 15:53:30 -04:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
ffloor.f64.ll
…
ffloor.ll
…
fix-frame-ptr-reg-copy-livein.ll
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
fix-sgpr-copies.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fix-vgpr-copies.mir
…
fix-wwm-vgpr-copy.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
flat_atomics_i64.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
flat_atomics.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
flat-address-space.ll
[AMDGPU] Avoid splitting FLAT offsets in unsafe ways
2020-07-17 11:44:10 +01:00
flat-error-unsupported-gpu-hsa.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
flat-for-global-subtarget-feature.ll
…
flat-load-clustering.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
flat-offset-bug.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
flat-scratch-reg.ll
…
floor.ll
…
fma-combine.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fma.f64.ll
…
fma.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
fmac.sdwa.ll
…
fmad-formation-fmul-distribute-denormal-mode.ll
DAG: Fix wrong legality check for ISD::FMAD
2020-04-13 10:25:39 -07:00
fmad.ll
…
fmax3.f64.ll
…
fmax3.ll
…
fmax_legacy.f16.ll
…
fmax_legacy.f64.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
fmax_legacy.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
fmax.ll
…
fmaxnum.f64.ll
…
fmaxnum.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmaxnum.r600.ll
…
fmed3.ll
…
fmin3.ll
…
fmin_fmax_legacy.amdgcn.ll
…
fmin_legacy.f16.ll
…
fmin_legacy.f64.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
fmin_legacy.ll
[llvm] Fix yet more missing FileCheck colons
2020-04-13 10:49:19 -06:00
fmin.ll
…
fminnum.f64.ll
AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul
2020-04-23 15:24:13 -04:00
fminnum.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fminnum.r600.ll
…
fmul64.ll
…
fmul-2-combine-multi-use.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmul.f16.ll
…
fmul.ll
…
fmuladd.f16.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fmuladd.f32.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fmuladd.f64.ll
[NFC][AMDGPU] Improve fused fmul+fadd tests.
2020-07-31 04:00:09 +03:00
fmuladd.v2f16.ll
[NFC][AMDGPU] Improve fused fmul+fadd tests.
2020-07-31 04:00:09 +03:00
fnearbyint.ll
…
fneg-combines.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
fneg-combines.si.ll
…
fneg-fabs.f16.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
…
fneg-fold-legalize-dag-increase-insts.ll
DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz
2019-12-31 22:49:51 -05:00
fneg.f16.ll
…
fneg.f64.ll
…
fneg.ll
…
fold_16bit_imm.mir
[AMDGPU] Fix FoldImmediate for 16 bit operand
2020-05-05 10:19:14 -07:00
fold_acc_copy_into_valu.mir
…
fold-cndmask.mir
…
fold-fi-mubuf.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
fold-fi-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-fmul-to-neg-abs.ll
…
fold-imm-copy.mir
AMDGPU: Fix visiting physreg dest users when folding immediate copies
2020-08-10 13:46:51 -04:00
fold-imm-f16-f32.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fold-immediate-operand-shrink-with-carry.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-output-mods.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fold-implicit-operand.mir
…
fold-multiple.mir
…
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
…
fold-over-exec.mir
…
fold-readlane.mir
…
fold-reload-into-exec.mir
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
fold-reload-into-m0.mir
AMDGPU: Disallow spill folding with m0 copies
2019-10-30 14:56:33 -07:00
fold-sgpr-copy.mir
[AMDGPU] Enable SGPR copy folding
2019-10-25 15:08:30 -07:00
fold-sgpr-multi-imm.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
fold-vgpr-copy.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
force-alwaysinline-lds-global-address-codegen.ll
…
force-alwaysinline-lds-global-address.ll
AMDGPU: Hack out noinline on functions using LDS globals
2020-04-02 14:12:07 -04:00
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll
…
fp_to_uint.f64.ll
…
fp_to_uint.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
fp-atomic-to-s_denormmode.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
fp-classify.ll
…
fpext-free.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fpext.f16.ll
…
fpext.ll
…
fpow.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
fptosi.f16.ll
AMDGPU: Simplify f16 to i64 custom lowering
2020-07-22 10:32:14 +02:00
fptoui.f16.ll
AMDGPU: Simplify f16 to i64 custom lowering
2020-07-22 10:32:14 +02:00
fptrunc.f16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
fptrunc.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
fract.f64.ll
…
fract.ll
…
frame-index-elimination.ll
[AMDGPU] Reuse register during frame index elimination
2020-03-20 00:19:15 -07:00
frame-lowering-entry-all-sgpr-used.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
frame-lowering-fp-adjusted.mir
[AMDGPU] Move frame pointer from s34 to s33
2020-03-19 15:35:16 -04:00
frem.ll
[AMDGPU] Propagate fast math flags in frem lowering
2020-08-05 09:09:38 +01:00
fshl.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
fshr.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
fsqrt.f64.ll
…
fsqrt.ll
AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)
2020-02-05 00:24:07 -05:00
fsub64.ll
…
fsub.f16.ll
…
fsub.ll
…
ftrunc.f64.ll
…
ftrunc.ll
…
function-args.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
function-call-relocs.ll
…
function-returns.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
gds-atomic.ll
…
gep-address-space.ll
…
gfx10-vop-literal.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
gfx902-without-xnack.ll
…
global_atomics_i64.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
global_atomics.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
global_smrd_cfg.ll
…
global_smrd.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
global-atomics-fp.ll
AMDGPU: Fix overriding global FP atomic feature predicates
2020-06-04 17:50:38 -04:00
global-constant.ll
[AMDGPU] Enable .rodata for amdpal os
2020-08-14 09:05:48 +02:00
global-directive.ll
…
global-extload-i16.ll
…
global-smrd-unknown.ll
…
global-variable-relocs.ll
…
gv-const-addrspace.ll
…
gv-offset-folding.ll
…
gws-hazards.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
half.ll
[Scheduling] Create the missing dependency edges for store cluster
2020-08-07 04:58:03 +00:00
hard-clauses.mir
[AMDGPU] Fix assertion failure in SIInsertHardClauses
2020-05-15 15:49:52 +01:00
hazard-buffer-store-v-interp.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard-hidden-bundle.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard-in-bundle.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard-inlineasm.mir
…
hazard-kill.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hoist-cond.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
hsa-default-device.ll
…
hsa-fp-mode.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
hsa-func-align.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-func.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-deduce-ro-arg.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-enqueue-kernel-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-enqueue-kernel.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-from-llvm-ir-full-v3.ll
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
hsa-metadata-from-llvm-ir-full.ll
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
hsa-metadata-hidden-args-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-hidden-args.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-hostcall-absent-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-hostcall-absent.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-hostcall-present-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-hostcall-present.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-images-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-images.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-invalid-ocl-version-1-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-invalid-ocl-version-1.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-invalid-ocl-version-2-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-invalid-ocl-version-2.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-invalid-ocl-version-3-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-invalid-ocl-version-3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-kernel-code-props-v3.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-kernel-code-props.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-metadata-wavefrontsize.ll
…
hsa-note-no-func.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
hsa.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
huge-number-operand-folds.mir
AMDGPU: Fix failures from overflowing uint8_t number of operands
2020-07-23 15:39:33 -04:00
huge-private-buffer.ll
…
i1_copy_phi_with_phi_incoming_value.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
i1-copies-rpo.mir
…
i1-copy-from-loop.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
i1-copy-phi.ll
…
i8-to-double-to-float.ll
…
icmp64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
idiv-licm.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
idot2.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
idot4s.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
idot4u.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
idot8s.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
idot8u.ll
[DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG
2020-07-29 18:10:59 +01:00
illegal-sgpr-to-vgpr-copy.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
image_ls_mipmap_zero.ll
…
image-attributes.ll
…
image-load-d16-tfe.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
image-resource-id.ll
…
image-schedule.ll
…
img-nouse-adjust.ll
…
imm16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
imm.ll
[AMDGPU] Regenerate immediate constant tests
2020-02-19 18:58:44 +00:00
immv216.ll
AMDGPU: Don't use 16-bit FP inline constants in integer operands
2020-06-17 19:14:10 -04:00
implicit-def-muse.ll
…
indirect-addressing-si-gfx9.ll
[AMDGPU] Always expand ext/insertelement with divergent idx
2020-05-20 15:51:29 -07:00
indirect-addressing-si-noopt.ll
[SDAG] fold extract_vector_elt with undef index
2019-10-25 19:27:26 -04:00
indirect-addressing-si-pregfx9.ll
[AMDGPU] Always expand ext/insertelement with divergent idx
2020-05-20 15:51:29 -07:00
indirect-addressing-si.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
indirect-addressing-term.ll
[AMDGPU] Do not use undef on indirect source
2020-07-30 10:41:59 -07:00
indirect-call.ll
AMDGPU: Fix fixed ABI SGPR arguments
2020-07-06 09:01:18 -04:00
indirect-private-64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
infer-addrpace-pipeline.ll
…
infer-uniform-load-shader.ll
AMDGPU: Fix not using scalar loads for global reads in shaders
2020-06-02 09:49:23 -04:00
infinite-loop-evergreen.ll
…
infinite-loop.ll
[AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation
2020-07-17 11:48:57 +09:00
inline-asm.ll
AMDGPU: Analyze divergence of inline asm
2020-02-03 12:42:16 -08:00
inline-attr.ll
AMDGPU: Stop setting attributes based on TargetOptions
2020-03-27 13:13:43 -07:00
inline-calls.ll
…
inline-constraints.ll
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
2020-07-02 17:20:15 +03:00
inline-maxbb.ll
…
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll
…
InlineAsmCrash.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
input-mods.ll
…
insert_subreg.ll
…
insert_vector_dynelt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
insert_vector_elt.ll
AMDGPU/GlobalISel: Match andn2/orn2 for more types
2020-08-14 13:18:03 -04:00
insert_vector_elt.v2i16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
insert_vector_elt.v2i16.subtest-saddr.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
insert-branch-w32.mir
[AMDGPU] Make sure to fix implicit operands on insertBranch
2020-06-24 16:50:48 +01:00
insert-skip-from-vcc.mir
[AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation
2020-07-17 11:48:57 +09:00
insert-skips-flat-vmem.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
insert-skips-gws.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
insert-skips-ignored-insts.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
insert-skips-kill-uncond.mir
[AMDGPU] Unify early PS termination blocks
2020-07-03 09:58:05 +09:00
insert-subvector-unused-scratch.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
insert-waitcnts-callee.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
insert-waitcnts-exp.mir
…
inserted-wait-states.mir
[AMDGPU] Removed s_mov_regrd and mov_fed opcodes
2020-07-17 19:52:54 +03:00
internalize.ll
…
invalid-addrspacecast.ll
AMDGPU: Lower addrspacecast to 32-bit constant
2020-05-08 10:46:00 -04:00
invalid-alloca.ll
Infer alignment of unmarked loads in IR/bitcode parsing.
2020-05-14 13:03:50 -07:00
invariant-load-no-alias-store.ll
…
invert-br-undef-vcc.mir
…
ipra-regmask.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
ipra.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-stack-alignment.ll
…
kernel-args.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
kernel-argument-dag-lowering.ll
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
kill-infinite-loop.ll
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
known-never-nan.ll
…
known-never-snan.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
knownbits-recursion.ll
…
large-alloca-compute.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
large-alloca-graphics.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
lcssa-optnone.ll
…
lds_atomic_f32.ll
…
lds-alignment.ll
…
lds-bounds.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
lds-branch-vmem-hazard.mir
…
lds-global-non-entry-func.ll
AMDGPU: Don't hard error on LDS globals in functions
2020-03-11 15:34:11 -04:00
lds-initializer.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll
…
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-relocs.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
lds-size.ll
…
lds-zero-initializer.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
legalize-fp-load-invariant.ll
…
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir
…
lit.local.cfg
…
literals.ll
…
liveness.mir
…
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.csub.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.atomic.dec.ll
…
llvm.amdgcn.atomic.fadd.ll
AMDGPU: Fix overriding global FP atomic feature predicates
2020-06-04 17:50:38 -04:00
llvm.amdgcn.atomic.inc.ll
…
llvm.amdgcn.ballot.i32.ll
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
llvm.amdgcn.buffer.atomic.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.amdgcn.buffer.load.dwordx3.ll
…
llvm.amdgcn.buffer.load.format.d16.ll
…
llvm.amdgcn.buffer.load.format.ll
…
llvm.amdgcn.buffer.load.ll
…
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.buffer.store.format.d16.ll
…
llvm.amdgcn.buffer.store.format.ll
…
llvm.amdgcn.buffer.store.ll
…
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.pk.i16.ll
…
llvm.amdgcn.cvt.pk.u16.ll
…
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.div.scale.ll
…
llvm.amdgcn.ds.append.ll
AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands
2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.bpermute.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.consume.ll
AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands
2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.gws.barrier.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
llvm.amdgcn.ds.gws.init.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.p.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.ordered.add.ll
AMDGPU: Don't error on ds.ordered intrinsic in function
2020-01-24 13:06:44 -08:00
llvm.amdgcn.ds.ordered.swap.ll
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
2020-01-14 19:26:15 -05:00
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll
[AMDGPU] Strengthen export cluster ordering
2020-05-13 23:07:37 +09:00
llvm.amdgcn.exp.prim.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fmad.ftz.f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.fmad.ftz.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.a16.encode.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.atomic.dim.ll
AMDGPU: Add/Fix tests for image atomic intrinsic.
2020-03-05 12:18:15 -05:00
llvm.amdgcn.image.d16.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.dim.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.gather4.d16.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.getlod.dim.ll
…
llvm.amdgcn.image.load.a16.d16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.load.a16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.msaa.load.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.image.nsa.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer
2020-05-05 15:49:09 +01:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.image.sample.g16.encode.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
llvm.amdgcn.image.sample.ltolz.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.o.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
llvm.amdgcn.implicitarg.ptr.ll
AMDGPU: Fix DAG divergence for implicit function arguments
2020-05-19 18:11:34 -04:00
llvm.amdgcn.init.exec.ll
…
llvm.amdgcn.init.exec.wave32.ll
…
llvm.amdgcn.interp.f16.ll
…
llvm.amdgcn.interp.ll
…
llvm.amdgcn.is.private.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.is.shared.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.kill.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.ll
AMDGPU: Fix lit test checks with dag option
2019-11-28 10:01:06 +00:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Fixed dpp test. NFC.
2019-11-13 16:38:54 -08:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
…
llvm.amdgcn.mul.u24.ll
…
llvm.amdgcn.permlane.ll
AMDGPU/GlobalISel: Select permlane16/permlanex16
2020-01-29 17:55:31 -05:00
llvm.amdgcn.ps.live.ll
…
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.fadd.ll
AMDGPU: Define raw/struct variants of buffer atomic fadd
2020-08-06 13:36:19 -04:00
llvm.amdgcn.raw.buffer.atomic.ll
[AMDGPU] add buffer_atomic_swap for float
2020-08-06 09:45:48 +08:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.buffer.load.format.ll
…
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] New SIInsertHardClauses pass
2020-05-14 18:54:49 +01:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
…
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.readfirstlane.ll
…
llvm.amdgcn.readlane.ll
…
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
llvm.amdgcn.s.buffer.load.ll
AMDGPU: Fix broken check lines
2020-04-02 18:52:49 -04:00
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg
2020-07-28 21:34:50 -04:00
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
…
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.sdot8.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.sendmsg.ll
…
llvm.amdgcn.set.inactive.ll
…
llvm.amdgcn.sffbh.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.softwqm.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
llvm.amdgcn.sqrt.f16.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.sqrt.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
AMDGPU: Define raw/struct variants of buffer atomic fadd
2020-08-06 13:36:19 -04:00
llvm.amdgcn.struct.buffer.atomic.ll
[AMDGPU] add buffer_atomic_swap for float
2020-08-06 09:45:48 +08:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.load.ll
…
llvm.amdgcn.struct.buffer.store.format.d16.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.format.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.ll
…
llvm.amdgcn.struct.tbuffer.load.d16.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.load.d16.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.load.dwordx3.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.load.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.store.d16.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.store.dwordx3.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.store.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll
…
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wavefrontsize.ll
…
llvm.amdgcn.workgroup.id.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.amdgcn.workitem.id.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.amdgcn.wqm.vote.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote
2020-01-07 10:15:29 -05:00
llvm.amdgcn.writelane.ll
…
llvm.ceil.f16.ll
…
llvm.cos.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.exp2.f16.ll
…
llvm.exp2.ll
…
llvm.floor.f16.ll
…
llvm.fma.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.fmuladd.f16.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.log2.f16.ll
…
llvm.log2.ll
…
llvm.log10.f16.ll
…
llvm.log10.ll
…
llvm.log.f16.ll
…
llvm.log.ll
…
llvm.maxnum.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.memcpy.ll
[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr
2020-02-03 22:49:30 +00:00
llvm.minnum.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.mulo.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.pow.ll
…
llvm.powi.ll
AMDGPU: Fix promoting f16 fpowi with legal f16
2020-07-17 11:29:05 -04:00
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
…
llvm.rint.f64.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.rint.ll
…
llvm.round.f64.ll
[NFC][Test] Format the test with script update_llc_test_checks.py
2020-08-07 10:22:38 +00:00
llvm.round.ll
…
llvm.sin.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.sin.ll
[AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS
2020-05-31 05:21:55 +01:00
llvm.sqrt.f16.ll
…
llvm.trunc.f16.ll
…
lo16-32bit-physreg-copy.mir
[AMDGPU] fix copies between 32 and 16 bit
2020-05-04 08:54:22 -07:00
lo16-hi16-illegal-copy.mir
[AMDGPU] Drop 16 bit subreg suffixes on print
2020-05-06 08:14:10 -07:00
lo16-hi16-physreg-copy.mir
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
lo16-lo16-physreg-copy-agpr.mir
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
lo16-lo16-physreg-copy-sgpr.mir
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll
…
load-constant-i8.ll
…
load-constant-i16.ll
…
load-constant-i32.ll
…
load-constant-i64.ll
…
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
…
load-global-i8.ll
…
load-global-i16.ll
…
load-global-i32.ll
…
load-global-i64.ll
…
load-hi16.ll
[AMDGPU] Define 16 bit VGPR subregs
2020-03-31 11:49:06 -07:00
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-f64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i1.ll
…
load-local-i8.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i16.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i32.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-i64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-select-ptr.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
load-weird-sizes.ll
…
local-64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
local-atomics64.ll
…
local-atomics-fp.ll
…
local-atomics.ll
…
local-memory.amdgcn.ll
[AMDGPU] Bundle loads before post-RA scheduler
2020-01-24 11:33:38 -08:00
local-memory.ll
…
local-memory.r600.ll
…
local-stack-slot-offset.ll
…
loop_break.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
loop_exit_with_xor.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
loop_header_nopred.mir
[MBP] Avoid tail duplication if it can't bring benefit
2019-12-06 09:53:53 -08:00
loop-address.ll
…
loop-idiom.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
loop-prefetch.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
lower-control-flow-other-terminators.mir
AMDGPU: Skip other terminators before inserting s_cbranch_exec[n]z
2020-07-24 16:51:59 -04:00
lower-kernargs.ll
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
lower-mem-intrinsics-threshold.ll
AMDGPU: Add flag to control mem intrinsic expansion
2020-02-03 14:26:01 -08:00
lower-mem-intrinsics.ll
AMDGPU: Implement getMemcpyLoopLoweringType
2020-03-30 22:21:01 +01:00
lower-range-metadata-intrinsic-call.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
lshl64-to-32.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
lshr.v2i16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
machine-cse-commute-target-flags.mir
AMDGPU: Support commuting register and global operand
2020-07-01 13:59:13 -04:00
macro-fusion-cluster-vcc-uses.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
mad24-get-global-id.ll
…
mad_64_32.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
mad_int24.ll
…
mad_uint24.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
mad-combine.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad-mix-hi.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad-mix-lo.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad-mix.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
mad.u16.ll
…
madak-inline-constant.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
madak.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
madmk.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
mai-hazards.mir
[AMDGPU] Fix MAI ld/st hazard handling
2020-08-14 17:07:37 -07:00
mai-inline.ll
…
max3.ll
…
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
max.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
mcp-overlap-after-propagation.mir
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
med3-no-simplify.ll
…
mem-builtins.ll
…
memcpy-fixed-align.ll
DAG: Don't pass 0 alignment value to allowsMisalignedMemoryAccesses
2020-08-13 09:33:17 -04:00
memcpy-inline-fails.ll
Revert "Disable memcpy-inline-fails.ll for windows"
2020-03-16 16:03:39 +01:00
memory_clause.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
memory_clause.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
memory-legalizer-amdpal.ll
[AMDGPU] Make generating cache invalidating instructions optional
2020-07-27 09:24:11 +02:00
memory-legalizer-atomic-cmpxchg.ll
…
memory-legalizer-atomic-fence.ll
…
memory-legalizer-atomic-insert-end.mir
llc: Change behavior of -mcpu with existing attribute
2020-01-07 10:10:25 -05:00
memory-legalizer-atomic-rmw.ll
…
memory-legalizer-invalid-addrspace.mir
…
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-load.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
memory-legalizer-local.mir
…
memory-legalizer-mesa3d.ll
…
memory-legalizer-multiple-mem-operands-atomics.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
memory-legalizer-region.mir
…
memory-legalizer-store-infinite-loop.ll
…
memory-legalizer-store.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
merge-image-load-gfx10.mir
SILoadStoreOptimizer: add support for GFX10 image instructions
2020-07-08 19:15:46 +01:00
merge-image-load.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
merge-image-sample-gfx10.mir
SILoadStoreOptimizer: add support for GFX10 image instructions
2020-07-08 19:15:46 +01:00
merge-image-sample.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
merge-load-store-physreg.mir
…
merge-load-store-vreg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
merge-load-store.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
merge-m0.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
merge-out-of-order-ldst.ll
[AMDGPU] Fix crash in SILoadStoreOptimizer
2020-04-02 10:26:47 -07:00
merge-out-of-order-ldst.mir
[AMDGPU] Fix crash in SILoadStoreOptimizer
2020-04-02 10:26:47 -07:00
merge-store-crash.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
merge-store-usedef.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
merge-stores.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
merge-tbuffer.mir
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
mesa3d.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mesa_regression.ll
…
mfma-loop.ll
[AMDGPU] Added label to test. NFC.
2020-04-03 11:36:32 -07:00
min3.ll
…
min.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
mir-print-dead-csr-fi.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
misched-killflags.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
missing-store.ll
…
mixed_wave32_wave64.ll
…
mixed-wave32-wave64.ll
…
mode-register.mir
[AMDGPU] Avoid redundant mode register writes
2020-06-24 14:11:29 +01:00
move-addr64-rsrc-dead-subreg-writes.ll
…
move-to-valu-atomicrmw.ll
…
move-to-valu-worklist.ll
…
movreld-bug.ll
AMDGPU: Add gfx9 run lines to a testcase
2020-01-03 15:25:50 -05:00
movrels-bug.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
mubuf-legalize-operands.ll
[AMDGPU] Remove unnecessary s_waitcnt between VMEM loads
2020-05-01 10:10:23 +01:00
mubuf-legalize-operands.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
mubuf-offset-private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mubuf-shader-vgpr.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
mubuf.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
mul24-pass-ordering.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
mul_int24.ll
…
mul_uint24-amdgcn.ll
[AMDGPU] Fix bundle scheduling
2020-01-09 15:56:36 -08:00
mul_uint24-r600.ll
…
mul.i16.ll
…
mul.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
multi-divergent-exit-region.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
[AMDGPU] Enable structurizer workarounds by default
2020-06-09 13:14:15 +05:30
nand.ll
…
nested-calls.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
nested-loop-conditions.ll
[AMDGPU] Enable structurizer workarounds by default
2020-06-09 13:14:15 +05:30
no-bundle-asm.ll
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
no-remat-indirect-mov.mir
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
no-shrink-extloads.ll
…
non-entry-alloca.ll
AMDGPU: Correct prolog SP initialization logic
2020-08-05 15:47:53 -04:00
noop-shader-O0.ll
…
nop-data.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
nop-fold.mir
AMDGPU: Don't fold S_NOPs with implicit operands
2019-10-30 14:40:56 -07:00
nor.ll
…
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
nsa-vmem-hazard.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
nullptr.ll
AMDGPU: Fix wrong null value for private address space
2020-05-26 16:35:13 -04:00
occupancy-levels.ll
AMDGPU: Fix computation for getOccupancyWithLocalMemSize
2020-03-03 17:15:57 -05:00
offset-split-flat.ll
[AMDGPU] Avoid splitting FLAT offsets in unsafe ways
2020-07-17 11:44:10 +01:00
offset-split-global.ll
[AMDGPU] Avoid splitting FLAT offsets in unsafe ways
2020-07-17 11:44:10 +01:00
omod-nsz-flag.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
omod.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
opencl-image-metadata.ll
…
opencl-printf-no-hostcall.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
opencl-printf.ll
…
operand-folding.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
operand-spacing.ll
…
opt-pipeline.ll
[LPM] Port CGProfilePass from NPM to LPM
2020-07-10 09:04:51 -07:00
opt-sgpr-to-vgpr-copy.mir
…
optimize-exec-copies-extra-insts-after-copy.mir
AMDGPU: Optimize copies to exec with other insts after exec def
2020-07-28 21:34:50 -04:00
optimize-exec-mask-pre-ra-loop-phi.mir
AMDGPU: Check for other defs when folding conditions into s_andn2_b64
2020-07-28 16:36:23 -04:00
optimize-exec-masking-pre-ra.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-exec-masking-strip-terminator-bits.mir
AMDGPU: Don't assume there is only one terminator copy
2020-07-28 20:22:38 -04:00
optimize-if-exec-masking.mir
…
optimize-negated-cond-exec-masking-wave32.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond-exec-masking.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
or3.ll
…
or.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
pack.v2f16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
pack.v2i16.ll
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
packed-op-sel.ll
[AMDGPU] Fix bundle scheduling
2020-01-09 15:56:36 -08:00
packetizer.ll
…
pal-userdata-regs.ll
[AMDGPU] Fixed incorrect PAL metadata register naming
2020-05-21 22:13:19 +01:00
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-sgpr-to-vgpr-spills.ll
RegAllocFast: Record internal state based on register units
2020-06-03 16:51:46 -04:00
partial-shift-shrink.ll
…
partially-dead-super-register-immediate.ll
…
peephole-opt-regseq-removal.mir
…
pei-reg-scavenger-position.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
pei-scavenge-sgpr-carry-out.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
pei-scavenge-sgpr-gfx9.mir
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
pei-scavenge-sgpr.mir
[AMDGPU] Enable base pointer.
2020-05-17 16:13:55 +05:30
pei-scavenge-vgpr-spill.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
perfhint.ll
[AMDGPU] Add some missing check prefixes and tweak test
2020-07-17 12:57:47 +01:00
permute.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
phi-elimination-assertion.mir
…
phi-elimination-end-cf.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
phi-vgpr-input-moveimm.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir
…
postra-bundle-memops.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
postra-machine-sink.mir
[AMDGPU] Fixed lane mask in test. NFC.
2020-04-15 15:26:53 -07:00
postra-norename.mir
…
power-sched-no-instr-sunit.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
predicate-dp4.ll
…
predicates.ll
…
preserve-hi16.ll
…
print-mir-custom-pseudo.ll
…
private-access-no-objects.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
private-element-size.ll
[SelectionDAG] Don't promote the alignment of allocas beyond the stack alignment.
2020-05-11 17:39:00 -07:00
private-memory-atomics.ll
…
private-memory-r600.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-addrspacecast.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-globals.ll
…
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
…
promote-alloca-mem-intrinsics.ll
…
promote-alloca-no-opts.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
promote-alloca-padding-size-estimate.ll
AMDGPU: Account for the size of LDS globals used through constant
2020-07-29 11:40:42 -04:00
promote-alloca-pointer-array.ll
[AMDGPU] Fixed promote alloca with ptr/int casts
2020-06-10 11:46:57 -07:00
promote-alloca-stored-pointer-value.ll
…
promote-alloca-to-lds-constantexpr-use.ll
AMDGPU: Account for the size of LDS globals used through constant
2020-07-29 11:40:42 -04:00
promote-alloca-to-lds-icmp.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-phi.ll
[NFC] GetUnderlyingObject -> getUnderlyingObject
2020-07-30 21:08:24 -07:00
promote-alloca-to-lds-select.ll
[ValueTracking, BasicAA] Don't simplify instructions
2020-06-21 16:31:07 +02:00
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-to-vector.ll
[AMDGPU] Bail alloca vectorization if GEP not found
2020-05-26 13:59:49 -07:00
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
promote-constOffset-to-imm.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
promote-constOffset-to-imm.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
propagate-attributes-bitcast-function.ll
…
propagate-attributes-clone.ll
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
2020-03-26 14:43:44 -07:00
propagate-attributes-single-set.ll
…
ptrmask.ll
DAG: Use correct pointer size for llvm.ptrmask
2020-05-18 16:46:11 -04:00
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
Regenerate bitcast test for upcoming patch.
2020-02-02 18:27:44 +00:00
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
rcp_iflag.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
rcp-pattern.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
read_register.ll
AMDGPU: Adjust test so it will work with GlobalISel
2019-12-27 19:37:39 -05:00
read-register-invalid-subtarget.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
read-register-invalid-type-i32.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
read-register-invalid-type-i64.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
readcyclecounter.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
readlane_exec0.mir
…
README
…
reassoc-scalar.ll
…
reduce-build-vec-ext-to-ext-build-vec.ll
…
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
DAG: Combine extract_vector_elt of concat_vectors
2020-04-06 09:26:29 -04:00
reg-coalescer-sched-crash.ll
…
regbank-reassign-wave64.mir
[AMDGPU] Make GCNRegBankReassign assign based on subreg banks
2020-08-04 12:54:44 +09:00
regbank-reassign.mir
[AMDGPU] Make GCNRegBankReassign assign based on subreg banks
2020-08-04 12:54:44 +09:00
regcoal-subrange-join-seg.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
regcoal-subrange-join.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
…
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
regcoalescing-remove-partial-redundancy-assert.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
register-count-comments.ll
…
rel32.ll
[amdgpu] Fix REL32 relocations with negative offsets.
2020-06-21 23:09:03 -04:00
remove-short-exec-branches-gpr-idx-mode.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
remove-short-exec-branches-mode-def.mir
AMDGPU: Don't run mode switches with exec 0
2020-06-02 13:47:48 -04:00
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
rename-independent-subregs.mir
[AMDGPU] Define 16 bit SGPR subregs
2020-04-16 10:31:39 -07:00
reorder-stores.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
reqd-work-group-size.ll
Recommit "[InstCombine] Negator: -(X << C) --> X * (-1 << C)"
2020-08-05 15:59:13 +03:00
reserve-vgpr-for-sgpr-spill.ll
[AMDGPU] Spill CSR VGPR which is reserved for SGPR spills
2020-07-28 11:53:02 -07:00
ret_jump.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
ret.ll
…
returnaddress.ll
AMDGPU/GlobalISel: Select llvm.returnaddress
2020-08-04 17:14:38 -04:00
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
…
rsq.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
s_addk_i32.ll
…
s_code_end.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
s_movk_i32.ll
…
s_mulk_i32.ll
…
sad.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
saddo.ll
AMDGPU: Make saturating add/sub legal for DAG path
2020-07-29 08:27:31 -04:00
saddsat.ll
[DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG
2020-07-29 18:10:59 +01:00
salu-to-valu.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
sampler-resource-id.ll
…
scalar_to_vector_v2x16.ll
…
scalar_to_vector.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
scalar-branch-missing-and-exec.ll
…
scalar-store-cache-flush.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
sched-assert-dead-def-subreg-use-other-subreg.mir
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
sched-assert-onlydbg-value-empty-region.mir
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
sched-crash-dbg-value.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sched-prefer-non-mfma.mir
[AMDGPU] prefer non-mfma in post-RA schedule
2020-07-29 12:17:50 -07:00
schedule-barrier-fpmode.mir
AMDGPU: Add missing test for s_denorm_mode scheduling
2020-05-28 11:07:22 -04:00
schedule-barrier.mir
…
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
…
schedule-kernel-arg-loads.ll
…
schedule-regpressure-limit2.ll
…
schedule-regpressure-limit3.ll
…
schedule-regpressure-limit-clustering.ll
[AMDGPU] Fix not rescheduling without clustering
2020-08-07 11:15:58 -07:00
schedule-regpressure-limit.ll
…
schedule-regpressure.mir
…
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
scheduler-handle-move-bundle.mir
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
scheduler-subrange-crash.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
scratch-buffer.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
scratch-simple.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
sdiv64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
sdiv.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
sdivrem24.ll
…
sdivrem64.r600.ll
AMDGPU: Enable integer division bypass
2020-02-19 17:50:19 -05:00
sdwa-gfx9.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sdwa-op64-test.ll
…
sdwa-ops.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sdwa-peephole-instr-gfx10.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sdwa-peephole-instr.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sdwa-peephole.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
sdwa-preserve.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sdwa-scalar-ops.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
sdwa-stack.mir
[AMDGPU] Inhibit SDWA if target instruction has FI
2020-08-13 11:34:28 -07:00
sdwa-vop2-64bit.mir
…
select64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select-constant-cttz.ll
[AMDGPU] Fix typos in performCtlz_CttzCombine()
2020-07-14 10:18:18 +01:00
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
select-i1.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
select-opt.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select-undef.ll
…
select-vectors.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
selectcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sendmsg-m0-hazard.mir
…
set-dx10.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
set-gpr-idx-peephole.mir
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
setcc64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-limit-load-shrink.ll
…
setcc-opt.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
setcc-sext.ll
…
setcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
seto.ll
…
setuo.ll
…
sext-divergence-driven-isel.ll
[AMDGPU] Enable SEXT divergence driven selection.
2020-03-17 17:30:11 +03:00
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sgpr-control-flow.ll
[NFC][Test] Format the test with script update_llc_test_checks.py
2020-08-07 10:22:38 +00:00
sgpr-copy-duplicate-operand.ll
…
sgpr-copy.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
sgpr-spill-partially-undef.mir
AMDGPU: Fix verifier error on spilling partially defined SGPRs
2020-07-28 20:01:57 -04:00
sgpr-spill-wrong-stack-id.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
sgpr-spill.mir
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
…
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
shift-i128.ll
Revert "[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size"
2020-07-17 12:20:37 +05:30
shift-select.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
shl_add_constant.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
shl_add_ptr_csub.ll
AMDGPU: Handle intrinsics in performMemSDNodeCombine
2020-08-12 10:04:53 -04:00
shl_add_ptr_global.ll
AMDGPU: Handle intrinsics in performMemSDNodeCombine
2020-08-12 10:04:53 -04:00
shl_add_ptr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
shl_add.ll
…
shl_or.ll
…
shl-add-to-add-shl.ll
…
shl.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
shl.v2i16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
shrink-add-sub-constant.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
shrink-carry.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
shrink-instructions-flags.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
shrink-insts-scalar-bit-ops.mir
AMDGPU: Fix verifier error with undef source producing s_bitset*
2020-08-05 14:42:20 -04:00
shrink-vop3-carry-out.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
si-annotate-cf-noloop.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
si-annotate-cfg-loop-assert.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
si-annotatecfg-multiple-backedges.ll
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
2020-02-03 07:02:05 -08:00
si-fix-sgpr-copies.mir
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
si-i1-copies.mir
…
si-instr-info-correct-implicit-operands.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
si-lower-control-flow-kill.ll
…
si-lower-control-flow-unreachable-block.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
si-lower-control-flow.mir
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
si-lower-i1-copies.mir
…
si-lower-sgpr-spills.mir
…
si-scheduler.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
si-sgpr-spill.ll
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
si-spill-cf.ll
…
si-spill-sgpr-stack.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
si-triv-disjoint-mem-access.ll
AMDGPU: Remove SIFixupVectorISel pass
2020-08-15 12:11:51 -04:00
si-vector-hang.ll
…
sibling-call.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
sign_extend.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
simplify-libcalls2.ll
[AMDGPU][NFC] Skip processing intrinsics that do not become real instructions
2020-06-09 03:45:33 +03:00
simplify-libcalls.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
simplifydemandedbits-recursion.ll
…
sint_to_fp.f64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
sint_to_fp.i64.ll
…
sint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sitofp.f16.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
skip-branch-taildup-ret.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
skip-branch-trap.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
skip-if-dead.ll
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
smed3.ll
…
smem-no-clause-coalesced.mir
…
smem-war-hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
sminmax.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sminmax.v2i16.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
smrd_vmem_war.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
smrd-fold-offset.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
smrd-gfx10.ll
…
smrd-vccz-bug.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
smrd.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
sopk-compares.ll
…
speculative-execution-freecasts.ll
SpeculativeExecution: fixed ingoring free execution
2020-02-20 14:45:02 +03:00
spill192.mir
AMDGPU: Fix spill/restore of 192-bit registers
2020-06-14 13:12:01 -04:00
spill_more_than_wavesize_csr_sgprs.ll
[AMDGPU] Spill more than wavesize CSR SGPRs
2020-07-01 07:40:47 +00:00
spill-agpr.ll
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
spill-agpr.mir
AMDGPU: Fix spilling of 96-bit AGPRs
2020-08-06 12:42:07 -04:00
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
spill-empty-live-interval.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
spill-m0.ll
RegAllocFast: Record internal state based on register units
2020-06-03 16:51:46 -04:00
spill-offset-calculation.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
spill-scavenge-offset.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
spill-special-sgpr.mir
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
spill-vgpr-to-agpr.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
spill-wide-sgpr.ll
[AMDGPU] Make SGPR spills exec mask agnostic
2020-06-03 12:34:26 +09:00
split-arg-dbg-value.ll
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
split-scalar-i64-add.ll
…
split-smrd.ll
…
split-vector-memoperand-offsets.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
splitkit-copy-bundle.mir
Unbundle KILL bundles in VirtRegRewriter
2020-08-10 11:58:37 -07:00
splitkit.mir
…
sra.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sram-ecc-default.ll
…
srem64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
srem.ll
…
srl.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sroa-before-unroll.ll
AMDGPU: Fix test in code directory
2020-06-01 13:26:51 -04:00
SRSRC-GIT-clobber-check.mir
For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer
2020-05-06 10:31:15 -04:00
ssubo.ll
…
ssubsat.ll
[DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG
2020-07-29 18:10:59 +01:00
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
stack-realign-kernel.ll
AMDGPU: Assume f32 denormals are enabled by default
2020-04-02 17:17:12 -04:00
stack-realign.ll
[AMDGPU] Fix FP/BP spills when MUBUF constant offset exceeded
2020-08-13 14:12:00 -07:00
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
store_typed.ll
…
store-barrier.ll
…
store-global.ll
…
store-hi16.ll
[AMDGPU] Avoid splitting FLAT offsets in unsafe ways
2020-07-17 11:44:10 +01:00
store-local.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
store-private.ll
…
store-v3i64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
store-vector-ptrs.ll
…
store-weird-sizes.ll
[Scheduling] Create the missing dependency edges for store cluster
2020-08-07 04:58:03 +00:00
stress-calls.ll
…
strict_fadd.f16.ll
AMDGPU: Select strict_fadd
2020-06-04 17:49:00 -04:00
strict_fadd.f32.ll
AMDGPU: Select strict_fadd
2020-06-04 17:49:00 -04:00
strict_fadd.f64.ll
AMDGPU: Select strict_fadd
2020-06-04 17:49:00 -04:00
strict_fma.f16.ll
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
strict_fma.f32.ll
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
strict_fma.f64.ll
AMDGPU: Select strict_fma
2020-06-04 17:49:00 -04:00
strict_fmul.f16.ll
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
strict_fmul.f32.ll
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
strict_fmul.f64.ll
AMDGPU: Select strict_fmul
2020-06-04 17:49:00 -04:00
strict_fsub.f16.ll
DAG: Handle expanding strict_fsub into fneg and strict_fadd
2020-07-21 16:17:10 -04:00
strict_fsub.f32.ll
DAG: Handle expanding strict_fsub into fneg and strict_fadd
2020-07-21 16:17:10 -04:00
strict_fsub.f64.ll
DAG: Handle expanding strict_fsub into fneg and strict_fadd
2020-07-21 16:17:10 -04:00
structurize1.ll
…
structurize.ll
…
sub_i1.ll
…
sub-zext-cc-zext-cc.ll
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
sub.i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
sub.ll
…
sub.v2i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
subreg_interference.mir
…
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
subreg-eliminate-dead.ll
…
subreg-intervals.mir
…
subreg-split-live-in-error.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
subreg-undef-def-with-other-subreg-defs.mir
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
subvector-test.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
switch-default-block-unreachable.ll
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
2020-07-11 16:33:38 +05:30
switch-unreachable.ll
[AMDGPU] add generated checks for some LIT tests
2020-03-03 11:47:05 +05:30
swizzle-export.ll
…
syncscopes.ll
…
tail-call-cgp.ll
…
tail-dup-bundle.mir
Process BUNDLE in tail duplication
2020-01-15 15:46:57 -08:00
tail-duplication-convergent.ll
…
target-cpu.ll
…
tex-clause-antidep.ll
…
texture-input-merge.ll
…
token-factor-inline-limit-test.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
transform-block-with-return-to-epilog.ll
[AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole
2020-08-13 21:52:41 +09:00
trap.ll
…
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
[AMDGPU] Fix CHECK lines
2020-04-03 10:07:21 +01:00
trunc-combine.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
…
trunc-store-i64.ll
Revert "[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size"
2020-07-17 12:20:37 +05:30
trunc-store-vec-i16-to-i8.ll
[AMDGPU] Expand vector trunc stores from i16 to i8
2020-04-07 21:47:45 -07:00
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
tti-unroll-prefs.ll
…
twoaddr-fma.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
twoaddr-mad.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
uaddo.ll
…
uaddsat.ll
[DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG
2020-07-29 18:10:59 +01:00
udiv64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
udiv.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
udivrem24.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
udivrem64.r600.ll
AMDGPU: Cleanup and generate 64-bit div tests
2020-01-20 17:19:39 -05:00
udivrem.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
uint_to_fp.f64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
uint_to_fp.i64.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
uint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uitofp.f16.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
umed3.ll
…
unaligned-load-store.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
undefined-physreg-sgpr-spill.mir
…
undefined-subreg-liverange.ll
Regenerate subreg liverange tests. NFC.
2020-07-06 13:58:25 +01:00
unhandled-loop-condition-assertion.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
uniform-branch-intrinsic-cond.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
uniform-cfg.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uniform-crash.ll
…
uniform-loop-inside-nonuniform.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
uniform-work-group-attribute-missing.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-nested-function-calls.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-prevent-attribute-propagation.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-propagate-attribute.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-recursion-test.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-test.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
unify-metadata.ll
…
unigine-liveness-crash.ll
…
unknown-processor.ll
…
unpack-half.ll
…
unroll.ll
[AMDGPU] Enable runtime unroll for LDS
2020-02-27 12:59:35 -08:00
unsupported-calls.ll
…
unsupported-cc.ll
…
unsupported-image-a16.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
unsupported-image-g16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
update-phi.ll
[AMDGPU] Fix AMDGPUUnifyDivergentExitNodes
2020-03-18 16:49:30 +01:00
urem64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
urem.ll
…
use-sgpr-multiple-times.ll
…
usubo.ll
…
usubsat.ll
[DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG
2020-07-29 18:10:59 +01:00
v1i64-kernel-arg.ll
…
v1024.ll
…
v_cndmask.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
v_cvt_pk_u8_f32.ll
…
v_mac_f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
v_mac.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
v_madak_f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
v_swap_b32.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
valu-i1.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
vccz-corrupt-bug-workaround.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
vcmpx-exec-war-hazard.mir
…
vcmpx-permlane-hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
vector_shuffle.packed.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca-bitcast.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
vector-alloca-limits.ll
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
vector-alloca.ll
…
vector-extract-insert.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
vector-legalizer-divergence.ll
…
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
vectorize-loads.ll
[AMDGPU] Disable sub-dword scralar loads IR widening
2020-04-10 08:20:49 -07:00
verify-sop.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
vertex-fetch-encoding.ll
…
vgpr-descriptor-waterfall-loop-idom-update.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
vgpr-spill-emergency-stack-slot-compute.ll
…
vgpr-spill-emergency-stack-slot.ll
[CodeGen] Ensure callers of CreateStackTemporary use sensible alignments
2020-06-09 08:10:17 +01:00
vgpr-tuple-allocation.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
visit-physreg-vgpr-imm-folding-bug.ll
AMDGPU: Fix visiting physreg dest users when folding immediate copies
2020-08-10 13:46:51 -04:00
vmem-to-salu-hazard.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vmem-vcc-hazard.mir
…
vop-shrink-frame-index.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink-non-ssa.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink.ll
…
vselect64.ll
…
vselect.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
[AMDGPU] Order pos exports before param exports
2020-05-12 23:02:23 +09:00
waitcnt-back-edge-loop.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
waitcnt-debug.mir
…
waitcnt-flat.ll
…
waitcnt-loop-irreducible.mir
…
waitcnt-loop-single-basic-block.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
waitcnt-looptest.ll
…
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
waitcnt-permute.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
waitcnt-preexisting.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
waitcnt-skip-meta.mir
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
waitcnt-vmem-waw.mir
AMDGPU: Move MIMG MMO check to verifier
2020-05-29 20:58:23 -04:00
waitcnt-vscnt.ll
…
waitcnt-vscnt.mir
[amdgpu] Fix scoreboard updating on s_waitcnt_vscnt.
2019-12-31 14:20:30 -05:00
waitcnt.mir
[AMDGPU] Fix wait counts in the presence of 16bit subregisters
2020-05-26 12:19:27 +03:00
wave32.ll
[AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation
2020-07-17 11:48:57 +09:00
wave_dispatch_regs.ll
…
widen_extending_scalar_loads.ll
Make IRBuilder automatically set alignment on load/store/alloca.
2020-04-13 13:43:14 -07:00
widen-smrd-loads.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
widen-vselect-and-mask.ll
…
wqm.ll
[AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
2020-07-15 11:02:35 +09:00
wqm.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
write_register.ll
AMDGPU: Split test function
2020-01-12 22:44:51 -05:00
write-register-vgpr-into-sgpr.ll
…
wrong-transalu-pos-fix.ll
…
wwm-reserved.ll
[AMDGPU] Add some missing -LABEL checks
2020-06-19 15:34:14 +01:00
xfail.r600.bitcast.ll
…
xnor.ll
…
xor3-i1-const.ll
…
xor3.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
xor_add.ll
…
xor.ll
…
zero_extend.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
zext-i64-bit-operand.ll
…
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.