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117 lines
4.3 KiB
LLVM
117 lines
4.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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define float @test_vrecpss_f32(float %a, float %b) {
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; CHECK: test_vrecpss_f32
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; CHECK: frecps {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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%1 = insertelement <1 x float> undef, float %a, i32 0
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%2 = insertelement <1 x float> undef, float %b, i32 0
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%3 = call <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float> %1, <1 x float> %2)
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%4 = extractelement <1 x float> %3, i32 0
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ret float %4
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}
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define double @test_vrecpsd_f64(double %a, double %b) {
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; CHECK: test_vrecpsd_f64
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; CHECK: frecps {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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%1 = insertelement <1 x double> undef, double %a, i32 0
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%2 = insertelement <1 x double> undef, double %b, i32 0
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%3 = call <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double> %1, <1 x double> %2)
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%4 = extractelement <1 x double> %3, i32 0
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ret double %4
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}
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declare <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float>, <1 x float>)
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declare <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double>, <1 x double>)
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define float @test_vrsqrtss_f32(float %a, float %b) {
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; CHECK: test_vrsqrtss_f32
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; CHECK: frsqrts {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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%1 = insertelement <1 x float> undef, float %a, i32 0
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%2 = insertelement <1 x float> undef, float %b, i32 0
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%3 = call <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float> %1, <1 x float> %2)
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%4 = extractelement <1 x float> %3, i32 0
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ret float %4
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}
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define double @test_vrsqrtsd_f64(double %a, double %b) {
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; CHECK: test_vrsqrtsd_f64
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; CHECK: frsqrts {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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%1 = insertelement <1 x double> undef, double %a, i32 0
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%2 = insertelement <1 x double> undef, double %b, i32 0
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%3 = call <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double> %1, <1 x double> %2)
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%4 = extractelement <1 x double> %3, i32 0
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ret double %4
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}
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declare <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float>, <1 x float>)
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declare <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double>, <1 x double>)
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define float @test_vrecpes_f32(float %a) {
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; CHECK: test_vrecpes_f32
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; CHECK: frecpe {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vrecpe.i = insertelement <1 x float> undef, float %a, i32 0
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%vrecpe1.i = tail call <1 x float> @llvm.arm.neon.vrecpe.v1f32(<1 x float> %vrecpe.i)
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%0 = extractelement <1 x float> %vrecpe1.i, i32 0
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ret float %0
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}
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define double @test_vrecped_f64(double %a) {
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; CHECK: test_vrecped_f64
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; CHECK: frecpe {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vrecpe.i = insertelement <1 x double> undef, double %a, i32 0
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%vrecpe1.i = tail call <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double> %vrecpe.i)
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%0 = extractelement <1 x double> %vrecpe1.i, i32 0
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ret double %0
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}
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declare <1 x float> @llvm.arm.neon.vrecpe.v1f32(<1 x float>)
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declare <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double>)
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define float @test_vrecpxs_f32(float %a) {
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; CHECK: test_vrecpxs_f32
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; CHECK: frecpx {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vrecpx.i = insertelement <1 x float> undef, float %a, i32 0
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%vrecpx1.i = tail call <1 x float> @llvm.aarch64.neon.vrecpx.v1f32(<1 x float> %vrecpx.i)
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%0 = extractelement <1 x float> %vrecpx1.i, i32 0
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ret float %0
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}
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define double @test_vrecpxd_f64(double %a) {
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; CHECK: test_vrecpxd_f64
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; CHECK: frecpx {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vrecpx.i = insertelement <1 x double> undef, double %a, i32 0
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%vrecpx1.i = tail call <1 x double> @llvm.aarch64.neon.vrecpx.v1f64(<1 x double> %vrecpx.i)
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%0 = extractelement <1 x double> %vrecpx1.i, i32 0
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ret double %0
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}
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declare <1 x float> @llvm.aarch64.neon.vrecpx.v1f32(<1 x float>)
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declare <1 x double> @llvm.aarch64.neon.vrecpx.v1f64(<1 x double>)
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define float @test_vrsqrtes_f32(float %a) {
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; CHECK: test_vrsqrtes_f32
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; CHECK: frsqrte {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vrsqrte.i = insertelement <1 x float> undef, float %a, i32 0
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%vrsqrte1.i = tail call <1 x float> @llvm.arm.neon.vrsqrte.v1f32(<1 x float> %vrsqrte.i)
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%0 = extractelement <1 x float> %vrsqrte1.i, i32 0
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ret float %0
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}
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define double @test_vrsqrted_f64(double %a) {
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; CHECK: test_vrsqrted_f64
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; CHECK: frsqrte {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vrsqrte.i = insertelement <1 x double> undef, double %a, i32 0
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%vrsqrte1.i = tail call <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double> %vrsqrte.i)
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%0 = extractelement <1 x double> %vrsqrte1.i, i32 0
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ret double %0
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}
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declare <1 x float> @llvm.arm.neon.vrsqrte.v1f32(<1 x float>)
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declare <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double>)
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