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114 lines
4.0 KiB
LLVM
114 lines
4.0 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev64D8:
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;CHECK: vrev64.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
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;CHECK: test_vrev64D16:
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;CHECK: vrev64.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i16> %tmp2
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}
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define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
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;CHECK: test_vrev64D32:
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;CHECK: vrev64.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x i32> %tmp2
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}
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define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
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;CHECK: test_vrev64Df:
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;CHECK: vrev64.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x float> %tmp2
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}
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define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
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;CHECK: test_vrev64Q8:
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;CHECK: vrev64.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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ret <16 x i8> %tmp2
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}
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define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
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;CHECK: test_vrev64Q16:
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;CHECK: vrev64.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i16> %tmp2
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}
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define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
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;CHECK: test_vrev64Q32:
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;CHECK: vrev64.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %tmp2
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}
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define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
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;CHECK: test_vrev64Qf:
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;CHECK: vrev64.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x float> %tmp2
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}
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define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev32D8:
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;CHECK: vrev32.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x i8> %tmp2
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}
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define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
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;CHECK: test_vrev32D16:
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;CHECK: vrev32.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i16> %tmp2
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}
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define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
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;CHECK: test_vrev32Q8:
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;CHECK: vrev32.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
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ret <16 x i8> %tmp2
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}
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define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
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;CHECK: test_vrev32Q16:
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;CHECK: vrev32.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i16> %tmp2
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}
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define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev16D8:
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;CHECK: vrev16.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x i8> %tmp2
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}
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define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
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;CHECK: test_vrev16Q8:
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;CHECK: vrev16.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i8> %tmp2
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}
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