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fc7c25abd8
There are three essentially different cases to handle:
* -O1, no LSE. The IR is expanded to ldxp/stxp and we need patterns to select
them.
* -O0, no LSE. We get G_ATOMIC_CMPXCHG, and need to produce CMP_SWAP_N
pseudos. The registers are all 64-bit so this is easy.
* LSE. We get G_ATOMIC_CMPXCHG and need to produce a CASP instruction with
XSeqPair registers.
The last case is by far the hardest, and and adds 128-bit GPR support as a
byproduct.
288 lines
9.7 KiB
TableGen
288 lines
9.7 KiB
TableGen
//=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 GlobalISel target pseudo instruction definitions. This is kept
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// separately from the other tablegen files for organizational purposes, but
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// share the same infrastructure.
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//
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//===----------------------------------------------------------------------===//
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class AArch64GenericInstruction : GenericInstruction {
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let Namespace = "AArch64";
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}
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// A pseudo to represent a relocatable add instruction as part of address
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// computation.
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def G_ADD_LOW : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$src, type2:$imm);
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let hasSideEffects = 0;
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}
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// Pseudo for a rev16 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_REV16 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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// Pseudo for a rev32 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_REV32 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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// Pseudo for a rev64 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_REV64 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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// Represents an uzp1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_UZP1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents an uzp2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_UZP2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a zip1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_ZIP1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a zip2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_ZIP2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a dup instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_DUP: AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$lane);
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let hasSideEffects = 0;
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}
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// Represents a lane duplicate operation.
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def G_DUPLANE8 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src, type1:$lane);
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let hasSideEffects = 0;
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}
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def G_DUPLANE16 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src, type1:$lane);
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let hasSideEffects = 0;
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}
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def G_DUPLANE32 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src, type1:$lane);
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let hasSideEffects = 0;
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}
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def G_DUPLANE64 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src, type1:$lane);
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let hasSideEffects = 0;
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}
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// Represents a trn1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_TRN1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a trn2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_TRN2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents an ext instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_EXT: AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
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let hasSideEffects = 0;
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}
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// Represents a vector G_ASHR with an immediate.
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def G_VASHR : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
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let hasSideEffects = 0;
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}
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// Represents a vector G_LSHR with an immediate.
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def G_VLSHR : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
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let hasSideEffects = 0;
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}
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// Represents an integer to FP conversion on the FPR bank.
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def G_SITOF : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_UITOF : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMEQ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type1:$src2);
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let hasSideEffects = 0;
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}
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def G_FCMGE : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type1:$src2);
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let hasSideEffects = 0;
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}
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def G_FCMGT : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type1:$src2);
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let hasSideEffects = 0;
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}
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def G_FCMEQZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMGEZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMGTZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMLEZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMLTZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def : GINodeEquiv<G_REV16, AArch64rev16>;
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def : GINodeEquiv<G_REV32, AArch64rev32>;
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def : GINodeEquiv<G_REV64, AArch64rev64>;
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def : GINodeEquiv<G_UZP1, AArch64uzp1>;
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def : GINodeEquiv<G_UZP2, AArch64uzp2>;
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def : GINodeEquiv<G_ZIP1, AArch64zip1>;
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def : GINodeEquiv<G_ZIP2, AArch64zip2>;
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def : GINodeEquiv<G_DUP, AArch64dup>;
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def : GINodeEquiv<G_DUPLANE8, AArch64duplane8>;
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def : GINodeEquiv<G_DUPLANE16, AArch64duplane16>;
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def : GINodeEquiv<G_DUPLANE32, AArch64duplane32>;
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def : GINodeEquiv<G_DUPLANE64, AArch64duplane64>;
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def : GINodeEquiv<G_TRN1, AArch64trn1>;
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def : GINodeEquiv<G_TRN2, AArch64trn2>;
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def : GINodeEquiv<G_EXT, AArch64ext>;
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def : GINodeEquiv<G_VASHR, AArch64vashr>;
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def : GINodeEquiv<G_VLSHR, AArch64vlshr>;
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def : GINodeEquiv<G_SITOF, AArch64sitof>;
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def : GINodeEquiv<G_UITOF, AArch64uitof>;
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def : GINodeEquiv<G_FCMEQ, AArch64fcmeq>;
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def : GINodeEquiv<G_FCMGE, AArch64fcmge>;
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def : GINodeEquiv<G_FCMGT, AArch64fcmgt>;
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def : GINodeEquiv<G_FCMEQZ, AArch64fcmeqz>;
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def : GINodeEquiv<G_FCMGEZ, AArch64fcmgez>;
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def : GINodeEquiv<G_FCMGTZ, AArch64fcmgtz>;
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def : GINodeEquiv<G_FCMLEZ, AArch64fcmlez>;
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def : GINodeEquiv<G_FCMLTZ, AArch64fcmltz>;
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def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
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// These are patterns that we only use for GlobalISel via the importer.
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def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
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(vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
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(f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
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let Predicates = [HasNEON] in {
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def : Pat<(v2f64 (sint_to_fp v2i32:$src)),
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(SCVTFv2f64 (SSHLLv2i32_shift V64:$src, 0))>;
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def : Pat<(v2f64 (uint_to_fp v2i32:$src)),
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(UCVTFv2f64 (USHLLv2i32_shift V64:$src, 0))>;
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def : Pat<(v2f32 (sint_to_fp v2i64:$src)),
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(FCVTNv2i32 (SCVTFv2f64 V128:$src))>;
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def : Pat<(v2f32 (uint_to_fp v2i64:$src)),
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(FCVTNv2i32 (UCVTFv2f64 V128:$src))>;
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def : Pat<(v2i64 (fp_to_sint v2f32:$src)),
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(FCVTZSv2f64 (FCVTLv2i32 V64:$src))>;
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def : Pat<(v2i64 (fp_to_uint v2f32:$src)),
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(FCVTZUv2f64 (FCVTLv2i32 V64:$src))>;
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def : Pat<(v2i32 (fp_to_sint v2f64:$src)),
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(XTNv2i32 (FCVTZSv2f64 V128:$src))>;
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def : Pat<(v2i32 (fp_to_uint v2f64:$src)),
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(XTNv2i32 (FCVTZUv2f64 V128:$src))>;
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}
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let Predicates = [HasNoLSE] in {
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def : Pat<(atomic_cmp_swap_8 GPR64:$addr, GPR32:$desired, GPR32:$new),
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(CMP_SWAP_8 GPR64:$addr, GPR32:$desired, GPR32:$new)>;
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def : Pat<(atomic_cmp_swap_16 GPR64:$addr, GPR32:$desired, GPR32:$new),
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(CMP_SWAP_16 GPR64:$addr, GPR32:$desired, GPR32:$new)>;
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def : Pat<(atomic_cmp_swap_32 GPR64:$addr, GPR32:$desired, GPR32:$new),
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(CMP_SWAP_32 GPR64:$addr, GPR32:$desired, GPR32:$new)>;
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def : Pat<(atomic_cmp_swap_64 GPR64:$addr, GPR64:$desired, GPR64:$new),
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(CMP_SWAP_64 GPR64:$addr, GPR64:$desired, GPR64:$new)>;
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}
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def : Pat<(int_aarch64_stlxp GPR64:$lo, GPR64:$hi, GPR64:$addr),
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(STLXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>;
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def : Pat<(int_aarch64_stxp GPR64:$lo, GPR64:$hi, GPR64:$addr),
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(STXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>;
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