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llvm-mirror/lib/Target/AArch64
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Nikita Popov e4e6f3eeff [AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476) 
This is a non-intrusive fix for
https://bugs.llvm.org/show_bug.cgi?id=51476 intended for backport
to the 13.x release branch. It expands on the current hack by
distinguishing between CmpValue of 0, 1 and 2, where 0 and 1 have
the obvious meaning and 2 means "anything else". The new optimization
from D98564 should only be performed for CmpValue of 0 or 1.

For main, I think we should switch the analyzeCompare() and
optimizeCompare() APIs to use int64_t instead of int, which is in
line with MachineOperand's notion of an immediate, and avoids this
problem altogether.

Differential Revision: https://reviews.llvm.org/D108076

(cherry picked from commit 81b106584f2baf33e09be2362c35c1bf2f6bfe94)
2021-08-18 20:07:23 -07:00
..
AsmParser [AArch64][SME] Add zero instruction 2021-07-27 08:35:45 +00:00
Disassembler [AArch64][SME] Add zero instruction 2021-07-27 08:35:45 +00:00
GISel [AArch64][GlobalISel] Fix constraining LDXPX intrinsic selection. 2021-07-27 12:13:56 -07:00
MCTargetDesc [AArch64][SME] Add zero instruction 2021-07-27 08:35:45 +00:00
TargetInfo
Utils [AArch64] Legalize MVT::i64x8 in DAG isel lowering 2021-08-02 15:45:58 +01:00
AArch64.h [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. 2021-05-07 17:01:27 -07:00
AArch64.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp [AArch64] Legalize MVT::i64x8 in DAG isel lowering 2021-08-02 15:45:58 +01:00
AArch64BranchTargets.cpp [AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey. 2021-04-23 10:07:25 +02:00
AArch64CallingConvention.cpp [clang][AArch64] Correctly align HFA arguments when passed on the stack 2021-04-15 22:58:14 +01:00
AArch64CallingConvention.h
AArch64CallingConvention.td IR/AArch64/X86: add "swifttailcc" calling convention. 2021-05-17 10:48:34 +01:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp [AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the 2021-03-01 13:52:57 -08:00
AArch64Combine.td [AArch64][GlobalISel] Add identity combines to post-legal combiner. 2021-07-26 15:17:11 -07:00
AArch64CompressJumpTables.cpp [AArch64] Don't try to compress jump tables if there are any inline asm instructions. 2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp [AArch64] Fix some coding standard issues related to namespace llvm 2021-05-05 15:27:16 -07:00
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp [AArch64][SVE] Break false dependencies for inactive lanes of unary operations 2021-07-26 15:01:21 +00:00
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp [AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32. 2021-07-12 15:30:42 -07:00
AArch64FrameLowering.cpp [AArch64] Fix Local Deallocation for Homogeneous Prolog/Epilog 2021-07-25 10:51:11 -07:00
AArch64FrameLowering.h [NFC] Fix a few whitespace issues and typos. 2021-07-04 11:49:58 +01:00
AArch64GenRegisterBankInfo.def AArch64: support i128 cmpxchg in GlobalISel. 2021-05-14 10:41:38 +01:00
AArch64InstrAtomics.td [AArch64] Fix i128 cmpxchg using ldxp/stxp. 2021-07-20 12:38:12 -07:00
AArch64InstrFormats.td [AArch64][SVE] Break false dependencies for inactive lanes of unary operations 2021-07-26 15:01:21 +00:00
AArch64InstrGISel.td AArch64: support i128 cmpxchg in GlobalISel. 2021-05-14 10:41:38 +01:00
AArch64InstrInfo.cpp [AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476) 2021-08-18 20:07:23 -07:00
AArch64InstrInfo.h [AArch64][SVE] Break false dependencies for inactive lanes of unary operations 2021-07-26 15:01:21 +00:00
AArch64InstrInfo.td [AArch64] Legalize MVT::i64x8 in DAG isel lowering 2021-08-02 15:45:58 +01:00
AArch64ISelDAGToDAG.cpp [SVE] Use reg+reg addressing mode for immediate offsets. 2021-07-26 16:24:16 +01:00
AArch64ISelLowering.cpp [AArch64][SVE] Fix assertion failure when lowering fixed length gather/scatter 2021-08-10 15:34:36 -07:00
AArch64ISelLowering.h [AArch64] Legalize MVT::i64x8 in DAG isel lowering 2021-08-02 15:45:58 +01:00
AArch64LoadStoreOptimizer.cpp Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier" 2021-06-23 09:54:16 +03:00
AArch64LowerHomogeneousPrologEpilog.cpp [CodeGen] Add missing includes (NFC) 2021-06-06 15:48:27 +02:00
AArch64MachineFunctionInfo.cpp [llvm] Rename StringRef _lower() method calls to _insensitive() 2021-06-25 00:22:01 +03:00
AArch64MachineFunctionInfo.h IR/AArch64/X86: add "swifttailcc" calling convention. 2021-05-17 10:48:34 +01:00
AArch64MacroFusion.cpp [AArch64] Fix some coding standard issues related to namespace llvm 2021-05-05 15:27:16 -07:00
AArch64MacroFusion.h [llvm] Add missing header guards (NFC) 2021-01-30 09:53:42 -08:00
AArch64MCInstLower.cpp [AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local 2021-05-07 09:44:26 -07:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp [NFCI] Move DEBUG_TYPE definition below #includes 2021-05-30 17:31:01 +08:00
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp [AArch64] Fix Copy Elemination for negative values 2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td AArch64: support i128 cmpxchg in GlobalISel. 2021-05-14 10:41:38 +01:00
AArch64RegisterInfo.cpp [AArch64][SME] Add load and store instructions 2021-07-16 10:11:10 +00:00
AArch64RegisterInfo.h Change materializeFrameBaseRegister() to return register 2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td [AArch64] Legalize MVT::i64x8 in DAG isel lowering 2021-08-02 15:45:58 +01:00
AArch64SchedA53.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedA55.td [AArch64] Update Cortex-A55 SchedModel to improve LDP scheduling 2021-07-16 12:00:57 +01:00
AArch64SchedA57.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedA57WriteRes.td [AARCH64] Improve accumulator forwarding for Cortex-A57 model 2021-01-04 10:58:43 +00:00
AArch64SchedA64FX.td [AArch64] Add Fujitsu A64FX scheduling model 2021-01-15 17:14:04 +09:00
AArch64SchedCyclone.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedExynosM3.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedExynosM4.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedExynosM5.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedFalkor.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SchedTSV110.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD 2021-02-18 16:55:16 +00:00
AArch64SelectionDAGInfo.h [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD 2021-02-18 16:55:16 +00:00
AArch64SIMDInstrOpt.cpp
AArch64SLSHardening.cpp [ARM][AArch64] SLSHardening: make non-comdat thunks possible 2021-05-20 17:07:05 +02:00
AArch64SMEInstrInfo.td [AArch64][SME] Add zero instruction 2021-07-27 08:35:45 +00:00
AArch64SpeculationHardening.cpp
AArch64StackTagging.cpp [NFC][asan] Always pass Dominator Trees into forAllReachableExits 2021-07-22 18:01:38 -07:00
AArch64StackTaggingPreRA.cpp [AArch64] Fix some coding standard issues related to namespace llvm 2021-05-05 15:27:16 -07:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries 2021-06-21 13:00:36 +01:00
AArch64Subtarget.h [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) 2021-07-12 13:28:10 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Break false dependencies for inactive lanes of unary operations 2021-07-26 15:01:21 +00:00
AArch64SystemOperands.td [AArch64][SME] Add system registers and related instructions 2021-07-20 08:06:26 +00:00
AArch64TargetMachine.cpp Fix typo in help text for -aarch64-enable-branch-targets. 2021-07-05 16:15:40 +01:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [Analysis] Add simple cost model for strict (in-order) reductions 2021-07-26 10:26:06 +01:00
AArch64TargetTransformInfo.h [Analysis] Add simple cost model for strict (in-order) reductions 2021-07-26 10:26:06 +01:00
CMakeLists.txt [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. 2021-05-07 17:01:27 -07:00
SMEInstrFormats.td [AArch64][SME] Add zero instruction 2021-07-27 08:35:45 +00:00
SVEInstrFormats.td [AArch64][SVE] Break false dependencies for inactive lanes of unary operations 2021-07-26 15:01:21 +00:00
SVEIntrinsicOpts.cpp [AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts 2021-07-20 14:17:30 +00:00