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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 21:42:54 +02:00
llvm-mirror/test/CodeGen
Alexei Starovoitov def314d5bf [bpf] Do not expand UNDEF SDNode during insn selection lowering
o Before this patch, BPF backend will expand UNDEF node
    to i64 constant 0.
  o For second pass of dag combiner, legalizer will run through
    each to-be-processed dag node.
  o If any new SDNode is generated and has an undef operand,
    dag combiner will put undef node, newly-generated constant-0 node,
    and any node which uses these nodes in the working list.
  o During this process, it is possible undef operand is
    generated again, and this will form an infinite loop
    for dag combiner pass2.
  o This patch allows UNDEF to be a legal type.

Signed-off-by: Yonghong Song <yhs@plumgrid.com>
Signed-off-by: Alexei Starovoitov <ast@plumgrid.com>
llvm-svn: 249718
2015-10-08 18:52:40 +00:00
..
AArch64 [AArch64] Fold a floating-point divide by power of two into fp conversion. 2015-10-07 17:51:37 +00:00
AMDGPU AMDGPU: Use explicit register size indirect pseudos 2015-10-07 00:42:51 +00:00
ARM [ARM] Promote helper function to SelectionDAG. 2015-10-07 17:28:58 +00:00
BPF [bpf] Do not expand UNDEF SDNode during insn selection lowering 2015-10-08 18:52:40 +00:00
CPP Fix CPP Backend for GEP API changes for opaque pointer types 2015-09-08 18:42:29 +00:00
Generic Make the default triple optional by allowing an empty string 2015-09-16 05:34:32 +00:00
Hexagon [Hexagon] Add an early if-conversion pass 2015-10-06 15:49:14 +00:00
Inputs DI: Require subprogram definitions to be distinct 2015-08-28 20:26:49 +00:00
Mips [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backend 2015-10-06 15:17:25 +00:00
MIR Fix PR 24724 - The implicit register verifier shouldn't assume certain operand 2015-09-10 14:04:34 +00:00
MSP430
NVPTX
PowerPC [PowerPC] Disable shrink wrapping 2015-09-30 17:29:03 +00:00
SPARC [SPARC] Switch to the Machine Scheduler. 2015-09-10 21:49:06 +00:00
SystemZ [SystemZ] Fix another assertion failure in tryBuildVectorShuffle 2015-10-08 17:46:59 +00:00
Thumb [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. 2015-10-05 14:49:54 +00:00
Thumb2 [ARM] Use correct half-precision functions in EABI mode 2015-10-07 16:58:49 +00:00
WebAssembly [WebAssembly] Switch to a more traditional assembly syntax 2015-10-06 00:27:55 +00:00
WinEH [WinEH] Remove unreachable blocks before preparation 2015-10-07 21:08:25 +00:00
X86 [WinEH] Relax assertion in the presence of stack realignment 2015-10-08 18:41:52 +00:00
XCore [opaque pointer type] Add textual IR support for explicit type parameter for global aliases 2015-09-11 03:22:04 +00:00