1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/test/CodeGen
Andrew Trick e163ac7185 MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the
interface and allow other strategies to select it.

llvm-svn: 173413
2013-01-25 04:01:04 +00:00
..
ARM Remove some register allocation order dependencies. 2013-01-19 00:03:32 +00:00
CPP
Generic For inline asm: 2013-01-11 18:12:39 +00:00
Hexagon Add indexed load/store instructions for offset validation check. 2013-01-17 18:42:37 +00:00
MBlaze
Mips [mips] Set flag neverHasSideEffects flag on some of the floating point instructions. 2013-01-25 00:20:39 +00:00
MSP430
NVPTX [NVPTX] Fix crash with unnamed struct arguments 2012-12-05 20:50:28 +00:00
PowerPC Restore reverted test case, this time with REQUIRES: asserts 2013-01-17 19:46:51 +00:00
R600 DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes 2013-01-02 22:13:01 +00:00
SI Add R600 backend 2012-12-11 21:25:42 +00:00
SPARC
Thumb Use the 'count' attribute to calculate the upper bound of an array. 2012-12-04 21:34:03 +00:00
Thumb2 Remove some register allocation order dependencies. 2013-01-19 00:03:32 +00:00
X86 MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the 2013-01-25 04:01:04 +00:00
XCore