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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
31 lines
1.2 KiB
YAML
31 lines
1.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple armv7-gnueabihf -run-pass instruction-select \
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# RUN: -verify-machineinstrs -o - %s | FileCheck %s
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---
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# Test that we constrain register classes of temporary virtual registers
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# defined by nested instructions built from a Dst Pattern
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#
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# G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where
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# COPY_TO_REGCLASS doesn't constrain its source register class. It exposes the
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# bug as we create a tmp reg for VTOSIZS' result and don't constrain its
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# register class as COPY_TO_REGCLASS' source (which is fine) nor as VTOSIZS'
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# destination (which is not).
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#
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# https://bugs.llvm.org/show_bug.cgi?id=35965
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name: test_fptosi
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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; CHECK-LABEL: name: test_fptosi
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; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
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; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg
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; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
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; CHECK: $r0 = COPY [[COPY1]]
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; CHECK: MOVPCLR 14, $noreg, implicit $r0
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%0:fprb(s32) = COPY $s0
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%1:gprb(s32) = G_FPTOSI %0(s32)
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$r0 = COPY %1(s32)
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MOVPCLR 14, $noreg, implicit $r0
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...
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