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llvm-mirror/test/CodeGen
Qiu Chaofan e2a03586ce [PowerPC] Support constrained conversion in SPE target
This patch adds support for constrained int/fp conversion between
signed/unsigned i32 and f32/f64.

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D82747
2020-07-13 12:18:36 +08:00
..
AArch64 [DAGCombiner] tighten fast-math constraints for fma fold 2020-07-12 08:51:49 -04:00
AMDGPU [AMDGPU] Move LowerSwitch pass to CodeGenPrepare. 2020-07-11 16:33:38 +05:30
ARC
ARM [ARM] Pass -verify-machineinstr to test and XFAIL until fixed. 2020-07-10 16:44:52 +01:00
AVR
BPF BPF: permit .maps section variables with typedef type 2020-07-12 09:42:25 -07:00
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC [PowerPC] Support constrained conversion in SPE target 2020-07-13 12:18:36 +08:00
RISCV [MC][RISCV] Set UseIntegratedAssembler to true 2020-07-12 21:04:48 -07:00
SPARC
SystemZ
Thumb
Thumb2
VE
WebAssembly [WebAssembly] Prefer v128.const for constant splats 2020-07-10 18:27:52 -07:00
WinCFGuard
WinEH
X86 [X86] Consistently use 128 as the PSHUFB/VPPERM index for zero 2020-07-12 10:52:43 -07:00
XCore