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7932e530a0
Now that unaligned access expansion should not attempt to produce i64 accesses, we can remove the hack in PreprocessISelDAG where this is done. This allows splitting i64 private accesses while allowing the new add nodes indexing the vector components can be folded with the base pointer arithmetic. llvm-svn: 268293
121 lines
5.9 KiB
LLVM
121 lines
5.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Extract the high bit of the 1st quarter
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; GCN-LABEL: {{^}}v_uextract_bit_31_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 31
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Extract the high bit of the 2nd quarter
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; GCN-LABEL: {{^}}v_uextract_bit_63_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 63
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Extract the high bit of the 3rd quarter
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; GCN-LABEL: {{^}}v_uextract_bit_95_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 95
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Extract the high bit of the 4th quarter
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; GCN-LABEL: {{^}}v_uextract_bit_127_i128:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}}
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; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]]
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ZERO0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO0]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 127
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Spans more than 2 dword boundaries
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; GCN-LABEL: {{^}}v_uextract_bit_34_100_i128:
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; GCN: buffer_load_dwordx2 v{{\[}}[[VAL2:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN: buffer_load_dword v[[VAL1:[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; GCN-DAG: v_lshl_b64 v{{\[}}[[SHLLO:[0-9]+]]:[[SHLHI:[0-9]+]]{{\]}}, v{{\[}}[[VAL2]]:[[VAL3]]{{\]}}, 30
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; GCN-DAG: v_lshrrev_b32_e32 v[[ELT1PART:[0-9]+]], 2, v[[VAL1]]
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; GCN-DAG: v_bfe_u32 v[[ELT2PART:[0-9]+]], v[[VAL3]], 2, 2{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
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; GCN-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[SHLLO]], v[[ELT1PART]]
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; GCN-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], 0, v[[SHLHI]]{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ELT2PART]]:[[ZERO]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: s_endpgm
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define void @v_uextract_bit_34_100_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 34
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%bit = and i128 %srl, 73786976294838206463
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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