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llvm-mirror/test/CodeGen
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Zarko Todorovski ecca945191 [AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above 
Adding usage of VSSRC and VSFRC when adding the live in registers on AIX.
This matches the behaviour of the rest of PPC Subtargets.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D104396
2021-07-07 09:18:20 -04:00
..
AArch64 [SVE] Fixed cast<FixedVectorType> on scalable vector in SelectionDAGBuilder::getUniformBase 2021-07-07 10:48:17 +01:00
AMDGPU [AMDGPU] Move atomic expand past infer address spaces 2021-07-06 15:53:32 -07:00
ARC
ARM [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
AVR Place the BlockAddress type in the address space of the containing function 2021-07-02 12:17:55 +01:00
BPF
Generic CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Hexagon [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
Inputs
Lanai CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
M68k [M68k][GloballSel] Lower outgoing return values in IRTranslator 2021-07-05 11:39:09 -07:00
Mips Mips/GlobalISel: Use accurate memory LLTs 2021-07-01 20:08:14 -04:00
MIR CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
MSP430
NVPTX tests/CodeGen: Use %python lit substitution when invoking python 2021-07-06 18:46:36 -07:00
PowerPC [AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above 2021-07-07 09:18:20 -04:00
RISCV [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno 2021-07-06 11:43:22 -07:00
SPARC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
SystemZ [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
Thumb CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Thumb2 [ARM] Transform a floating-point to fixed-point conversion to a VCVT_fix 2021-07-01 15:10:40 +01:00
VE [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization. 2021-06-29 11:00:11 -07:00
WebAssembly Revert "[WebAssembly] Implementation of global.get/set for reftypes in LLVM IR" 2021-07-02 11:49:51 +03:00
WinCFGuard
WinEH
X86 Recommit [ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers. 2021-07-06 12:16:05 -07:00
XCore Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00