mirror of
https://github.com/RPCS3/llvm-mirror.git
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532 lines
16 KiB
YAML
532 lines
16 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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---
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name: fneg_s32_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_s32_ss
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_FNEG %0
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$sgpr0 = COPY %1
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...
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---
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name: fneg_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fneg_s32_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FNEG %0
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$vgpr0 = COPY %1
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...
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---
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name: fneg_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_s32_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]]
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; GCN: $vgpr0 = COPY [[FNEG]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_FNEG %0
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$vgpr0 = COPY %1
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...
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---
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name: fneg_s16_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_s16_ss
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s16) = G_FNEG %1
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%3:sgpr(s32) = G_ANYEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: fneg_s16_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fneg_s16_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FNEG %1
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%3:vgpr(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: fneg_s16_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_s16_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]]
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16)
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; GCN: $vgpr0 = COPY [[COPY1]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FNEG %1
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%3:vgpr(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: fneg_v2s16_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fneg_v2s16_ss
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
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; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
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%0:sgpr(<2 x s16>) = COPY $sgpr0
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%1:sgpr(<2 x s16>) = G_FNEG %0
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$sgpr0 = COPY %1
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...
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---
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name: fneg_v2s16_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fneg_v2s16_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = G_FNEG %0
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$vgpr0 = COPY %1
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...
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---
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name: fneg_v2s16_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_v2s16_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; GCN: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]]
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; GCN: $vgpr0 = COPY [[FNEG]](<2 x s16>)
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%0:sgpr(<2 x s16>) = COPY $sgpr0
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%1:vgpr(<2 x s16>) = G_FNEG %0
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$vgpr0 = COPY %1
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...
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---
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name: fneg_s64_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fneg_s64_ss
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_FNEG %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: fneg_s64_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: fneg_s64_vv
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483648, implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e32_]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = G_FNEG %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: fneg_s64_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fneg_s64_vs
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GCN: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]]
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; GCN: S_ENDPGM 0, implicit [[FNEG]](s64)
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = G_FNEG %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: fneg_fabs_s32_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fneg_fabs_s32_ss
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: S_ENDPGM 0, implicit [[S_OR_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_FABS %0
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%2:sgpr(s32) = G_FNEG %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fneg_fabs_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fneg_fabs_s32_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_XOR_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FABS %0
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%2:vgpr(s32) = G_FNEG %0
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S_ENDPGM 0, implicit %2
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...
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---
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name: fneg_fabs_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_fabs_s32_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e32 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_XOR_B32_e32_]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_FABS %0
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%2:vgpr(s32) = G_FNEG %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fneg_fabs_s16_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_fabs_s16_ss
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_OR_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s16) = G_FABS %1
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%3:sgpr(s16) = G_FNEG %2
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%4:sgpr(s32) = G_ANYEXT %3
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$sgpr0 = COPY %4
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...
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|
|
---
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name: fneg_fabs_s16_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fneg_fabs_s16_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e32_]]
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; GCN: $vgpr0 = COPY [[COPY1]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FABS %1
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%3:vgpr(s16) = G_FNEG %2
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%4:sgpr(s32) = G_ANYEXT %3
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$vgpr0 = COPY %4
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...
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---
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name: fneg_fabs_s16_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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|
bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fneg_fabs_s16_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; GCN: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]]
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|
; GCN: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]]
|
|
; GCN: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16)
|
|
; GCN: $vgpr0 = COPY [[COPY1]](s32)
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
%1:sgpr(s16) = G_TRUNC %0
|
|
%2:sgpr(s16) = G_FNEG %1
|
|
%3:vgpr(s16) = G_FNEG %2
|
|
%4:sgpr(s32) = G_ANYEXT %3
|
|
$vgpr0 = COPY %4
|
|
...
|
|
|
|
---
|
|
name: fneg_fabs_v2s16_ss
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0_sgpr1
|
|
; GCN-LABEL: name: fneg_fabs_v2s16_ss
|
|
; GCN: liveins: $sgpr0_sgpr1
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
|
|
; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
|
; GCN: $sgpr0 = COPY [[S_OR_B32_]]
|
|
%0:sgpr(<2 x s16>) = COPY $sgpr0
|
|
%1:sgpr(<2 x s16>) = G_FABS %0
|
|
%2:sgpr(<2 x s16>) = G_FNEG %1
|
|
$sgpr0 = COPY %2
|
|
...
|
|
|
|
---
|
|
name: fneg_fabs_v2s16_vv
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: fneg_fabs_v2s16_vv
|
|
; GCN: liveins: $vgpr0
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
|
|
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
|
|
; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
|
|
%0:vgpr(<2 x s16>) = COPY $vgpr0
|
|
%1:vgpr(<2 x s16>) = G_FABS %0
|
|
%2:vgpr(<2 x s16>) = G_FNEG %0
|
|
$vgpr0 = COPY %2
|
|
...
|
|
|
|
---
|
|
name: fneg_fabs_v2s16_vs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
; GCN-LABEL: name: fneg_fabs_v2s16_vs
|
|
; GCN: liveins: $sgpr0
|
|
; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
|
|
; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147516416
|
|
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_XOR_B32_e32 [[S_MOV_B32_]](s16), [[FABS]](<2 x s16>), implicit $exec
|
|
; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]](<2 x s16>)
|
|
%0:sgpr(<2 x s16>) = COPY $sgpr0
|
|
%1:vgpr(<2 x s16>) = G_FABS %0
|
|
%2:vgpr(<2 x s16>) = G_FNEG %1
|
|
$vgpr0 = COPY %2
|
|
...
|
|
|
|
---
|
|
name: fneg_fabs_s64_ss
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0_sgpr1
|
|
; GCN-LABEL: name: fneg_fabs_s64_ss
|
|
; GCN: liveins: $sgpr0_sgpr1
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
|
|
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
|
|
; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
|
|
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
|
%1:sgpr(s64) = G_FABS %0
|
|
%2:sgpr(s64) = G_FNEG %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: fneg_fabs_s64_vv
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1
|
|
; GCN-LABEL: name: fneg_fabs_s64_vv
|
|
; GCN: liveins: $vgpr0_vgpr1
|
|
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
|
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483648, implicit $exec
|
|
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
|
|
; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
|
|
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e32_]], %subreg.sub1
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
|
|
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
|
%1:vgpr(s64) = G_FABS %0
|
|
%2:vgpr(s64) = G_FNEG %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: fneg_fabs_s64_vs
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0_sgpr1
|
|
; GCN-LABEL: name: fneg_fabs_s64_vs
|
|
; GCN: liveins: $sgpr0_sgpr1
|
|
; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
|
; GCN: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
|
|
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32(s32) = V_MOV_B32_e32 2147483648, implicit $exec
|
|
; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub1(s64)
|
|
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e32 [[COPY1]](s32), [[V_MOV_B32_e32_]](s32), implicit $exec
|
|
; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64)
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e32_]](s16), %subreg.sub1
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64)
|
|
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
|
%1:vgpr(s64) = G_FABS %0
|
|
%2:vgpr(s64) = G_FNEG %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|