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https://github.com/RPCS3/llvm-mirror.git
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62e22a5a7e
This adds the llvm.abs(), llvm.umin(), llvm.umax(), llvm.smin(), and llvm.smax() intrinsics specified in D81829. For SelectionDAG, the ISD opcodes and all the legalization and lowering already exist, so this just wires them up to the intrinsic in the SDAG builder and adds rudimentary tests. For GlobalISel only the min/max intrinsics are wired up, as llvm.abs() will require the addition of a G_ABS op, and corresponding legalization support. Differential Revision: https://reviews.llvm.org/D84125
105 lines
3.5 KiB
LLVM
105 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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declare i32 @llvm.umin.i32(i32, i32)
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declare i32 @llvm.umax.i32(i32, i32)
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declare i32 @llvm.smin.i32(i32, i32)
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declare i32 @llvm.smax.i32(i32, i32)
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declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
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define i32 @test_umin_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_umin_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.umin.i32(i32 %a, i32 %b)
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ret i32 %r
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}
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define i32 @test_umax_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_umax_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.umax.i32(i32 %a, i32 %b)
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ret i32 %r
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}
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define i32 @test_smin_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_smin_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.smin.i32(i32 %a, i32 %b)
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ret i32 %r
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}
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define i32 @test_smax_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_smax_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.smax.i32(i32 %a, i32 %b)
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ret i32 %r
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}
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define <4 x i32> @test_umin_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_umin_v4i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_min_u32_e32 v0, v0, v4
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; CHECK-NEXT: v_min_u32_e32 v1, v1, v5
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; CHECK-NEXT: v_min_u32_e32 v2, v2, v6
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; CHECK-NEXT: v_min_u32_e32 v3, v3, v7
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %r
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}
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define <4 x i32> @test_umax_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_umax_v4i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_max_u32_e32 v0, v0, v4
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; CHECK-NEXT: v_max_u32_e32 v1, v1, v5
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; CHECK-NEXT: v_max_u32_e32 v2, v2, v6
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; CHECK-NEXT: v_max_u32_e32 v3, v3, v7
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %r
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}
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define <4 x i32> @test_smin_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_smin_v4i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_min_i32_e32 v0, v0, v4
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; CHECK-NEXT: v_min_i32_e32 v1, v1, v5
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; CHECK-NEXT: v_min_i32_e32 v2, v2, v6
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; CHECK-NEXT: v_min_i32_e32 v3, v3, v7
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %r
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}
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define <4 x i32> @test_smax_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_smax_v4i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_max_i32_e32 v0, v0, v4
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; CHECK-NEXT: v_max_i32_e32 v1, v1, v5
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; CHECK-NEXT: v_max_i32_e32 v2, v2, v6
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; CHECK-NEXT: v_max_i32_e32 v3, v3, v7
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%r = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %r
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}
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