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147 lines
7.2 KiB
LLVM
147 lines
7.2 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX906 -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cedar -verify-machineinstrs < %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=juniper -verify-machineinstrs < %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=sumo -verify-machineinstrs < %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=barts -verify-machineinstrs < %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=caicos -verify-machineinstrs < %s
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; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=turks -verify-machineinstrs < %s
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declare float @llvm.fma.f32(float, float, float) nounwind readnone
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declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; FUNC-LABEL: {{^}}fma_f32:
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; SI: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}},
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; EG: FMA {{\*? *}}[[RES]]
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define amdgpu_kernel void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) {
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%r0 = load float, float addrspace(1)* %in1
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%r1 = load float, float addrspace(1)* %in2
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%r2 = load float, float addrspace(1)* %in3
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%r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fmac_to_3addr_f32:
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; GCN: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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define float @fmac_to_3addr_f32(float %r0, float %r1, float %r2) {
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%r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
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ret float %r3
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}
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; FUNC-LABEL: {{^}}fma_v2f32:
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; SI: v_fma_f32
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; SI: v_fma_f32
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; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}},
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; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]
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; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
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define amdgpu_kernel void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
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<2 x float> addrspace(1)* %in2, <2 x float> addrspace(1)* %in3) {
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%r0 = load <2 x float>, <2 x float> addrspace(1)* %in1
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%r1 = load <2 x float>, <2 x float> addrspace(1)* %in2
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%r2 = load <2 x float>, <2 x float> addrspace(1)* %in3
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%r3 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %r0, <2 x float> %r1, <2 x float> %r2)
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store <2 x float> %r3, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fma_v4f32:
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+$}}
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; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}},
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; EG-DAG: FMA {{\*? *}}[[RES]].X
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; EG-DAG: FMA {{\*? *}}[[RES]].Y
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; EG-DAG: FMA {{\*? *}}[[RES]].Z
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; EG-DAG: FMA {{\*? *}}[[RES]].W
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define amdgpu_kernel void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
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<4 x float> addrspace(1)* %in2, <4 x float> addrspace(1)* %in3) {
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%r0 = load <4 x float>, <4 x float> addrspace(1)* %in1
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%r1 = load <4 x float>, <4 x float> addrspace(1)* %in2
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%r2 = load <4 x float>, <4 x float> addrspace(1)* %in3
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%r3 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %r0, <4 x float> %r1, <4 x float> %r2)
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store <4 x float> %r3, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fma_commute_mul_inline_imm_f32
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; SI: v_fma_f32 {{v[0-9]+}}, {{v[0-9]+}}, 2.0, {{v[0-9]+}}
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define amdgpu_kernel void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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%in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %in.a.gep, align 4
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%b = load float, float addrspace(1)* %in.b.gep, align 4
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%fma = call float @llvm.fma.f32(float %a, float 2.0, float %b)
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store float %fma, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; FUNC-LABEL: @fma_commute_mul_s_f32
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define amdgpu_kernel void @fma_commute_mul_s_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b, float %b) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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%in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %in.a.gep, align 4
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%c = load float, float addrspace(1)* %in.b.gep, align 4
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%fma = call float @llvm.fma.f32(float %a, float %b, float %c)
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store float %fma, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; Without special casing the inline constant check for v_fmac_f32's
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; src2, this fails to fold the 1.0 into an fma.
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; FUNC-LABEL: {{^}}fold_inline_imm_into_fmac_src2_f32:
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; GFX906: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; GFX906: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
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; GFX906: v_add_f32_e32 [[TMP2:v[0-9]+]], [[A]], [[A]]
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; GFX906: v_fma_f32 v{{[0-9]+}}, [[TMP2]], -4.0, 1.0
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define amdgpu_kernel void @fold_inline_imm_into_fmac_src2_f32(float addrspace(1)* %out, float addrspace(1)* %a, float addrspace(1)* %b) nounwind {
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bb:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds float, float addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds float, float addrspace(1)* %b, i64 %tid.ext
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%gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%tmp = load volatile float, float addrspace(1)* %gep.a
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%tmp1 = load volatile float, float addrspace(1)* %gep.b
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%tmp2 = fadd contract float %tmp, %tmp
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%tmp3 = fmul contract float %tmp2, 4.0
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%tmp4 = fsub contract float 1.0, %tmp3
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%tmp5 = fadd contract float %tmp4, %tmp1
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%tmp6 = fadd contract float %tmp1, %tmp1
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%tmp7 = fmul contract float %tmp6, %tmp
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%tmp8 = fsub contract float 1.0, %tmp7
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%tmp9 = fmul contract float %tmp8, 8.0
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%tmp10 = fadd contract float %tmp5, %tmp9
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store float %tmp10, float addrspace(1)* %gep.out
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ret void
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}
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