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2b0231f519
This replaces most argument uses with loads, but for now not all. The code in SelectionDAG for calling convention lowering is actively harmful for amdgpu_kernel. It attempts to split the argument types into register legal types, which results in low quality code for arbitary types. Since all kernel arguments are passed in memory, we just want the raw types. I've tried a couple of methods of mitigating this in SelectionDAG, but it's easier to just bypass this problem alltogether. It's possible to hack around the problem in the initial lowering, but the real problem is the DAG then expects to be able to use CopyToReg/CopyFromReg for uses of the arguments outside the block. Exposing the argument loads in the IR also has the advantage that the LoadStoreVectorizer can merge them. I'm not sure the best approach to dealing with the IR argument list is. The patch as-is just leaves the IR arguments in place, so all the existing code will still compute the same kernarg size and pointlessly lowers the arguments. Arguably the frontend should emit kernels with an empty argument list in the first place. Alternatively a dummy array could be inserted as a single argument just to reserve space. This does have some disadvantages. Local pointer kernel arguments can no longer have AssertZext placed on them as the equivalent !range metadata is not valid on pointer typed loads. This is mostly bad for SI which needs to know about the known bits in order to use the DS instruction offset, so in this case this is not done. More importantly, this skips noalias arguments since this pass does not yet convert this to the equivalent !alias.scope and !noalias metadata. Producing this metadata correctly seems to be tricky, although this logically is the same as inlining into a function which doesn't exist. Additionally, exposing these loads to the vectorizer may result in degraded aliasing information if a pointer load is merged with another argument load. I'm also not entirely sure this is preserving the current clover ABI, although I would greatly prefer if it would stop widening arguments and match the HSA ABI. As-is I think it is extending < 4-byte arguments to 4-bytes but doesn't align them to 4-bytes. llvm-svn: 335650
216 lines
7.9 KiB
LLVM
216 lines
7.9 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; Make sure we don't turn the 32-bit argument load into a 16-bit
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; load. There aren't extending scalar lods, so that would require
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; using a buffer_load instruction.
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; FUNC-LABEL: {{^}}truncate_kernarg_i32_to_i16:
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; SI: s_load_dword s
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; SI: buffer_store_short v
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define amdgpu_kernel void @truncate_kernarg_i32_to_i16(i16 addrspace(1)* %out, i32 %arg) nounwind {
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%trunc = trunc i32 %arg to i16
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store i16 %trunc, i16 addrspace(1)* %out
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ret void
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}
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; It should be OK (and probably performance neutral) to reduce this,
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; but we don't know if the load is uniform yet.
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; FUNC-LABEL: {{^}}truncate_buffer_load_i32_to_i16:
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; SI: buffer_load_dword v
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; SI: buffer_store_short v
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define amdgpu_kernel void @truncate_buffer_load_i32_to_i16(i16 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
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%load = load i32, i32 addrspace(1)* %gep.in
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%trunc = trunc i32 %load to i16
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store i16 %trunc, i16 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_kernarg_i32_to_i8:
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; SI: s_load_dword s
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_kernarg_i32_to_i8(i8 addrspace(1)* %out, i32 %arg) nounwind {
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%trunc = trunc i32 %arg to i8
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store i8 %trunc, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_buffer_load_i32_to_i8:
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; SI: buffer_load_dword v
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_buffer_load_i32_to_i8(i8 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
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%load = load i32, i32 addrspace(1)* %gep.in
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%trunc = trunc i32 %load to i8
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store i8 %trunc, i8 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_kernarg_i32_to_i1:
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; SI: s_load_dword s
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_kernarg_i32_to_i1(i1 addrspace(1)* %out, i32 %arg) nounwind {
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%trunc = trunc i32 %arg to i1
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store i1 %trunc, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_buffer_load_i32_to_i1:
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; SI: buffer_load_dword v
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_buffer_load_i32_to_i1(i1 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i1, i1 addrspace(1)* %out, i32 %tid
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%load = load i32, i32 addrspace(1)* %gep.in
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%trunc = trunc i32 %load to i1
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store i1 %trunc, i1 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_kernarg_i64_to_i32:
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; SI: s_load_dword s
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; SI: buffer_store_dword v
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define amdgpu_kernel void @truncate_kernarg_i64_to_i32(i32 addrspace(1)* %out, [8 x i32], i64 %arg) nounwind {
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%trunc = trunc i64 %arg to i32
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store i32 %trunc, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_buffer_load_i64_to_i32:
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; SI: buffer_load_dword v
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; SI: buffer_store_dword v
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define amdgpu_kernel void @truncate_buffer_load_i64_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%load = load i64, i64 addrspace(1)* %gep.in
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%trunc = trunc i64 %load to i32
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store i32 %trunc, i32 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}srl_kernarg_i64_to_i32:
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; SI: s_load_dword s
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; SI: buffer_store_dword v
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define amdgpu_kernel void @srl_kernarg_i64_to_i32(i32 addrspace(1)* %out, [8 x i32], i64 %arg) nounwind {
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%srl = lshr i64 %arg, 32
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%trunc = trunc i64 %srl to i32
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store i32 %trunc, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}srl_buffer_load_i64_to_i32:
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; SI: buffer_load_dword v
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; SI: buffer_store_dword v
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define amdgpu_kernel void @srl_buffer_load_i64_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%load = load i64, i64 addrspace(1)* %gep.in
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%srl = lshr i64 %load, 32
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%trunc = trunc i64 %srl to i32
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store i32 %trunc, i32 addrspace(1)* %gep.out
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ret void
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}
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; Might as well reduce to 8-bit loads.
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; FUNC-LABEL: {{^}}truncate_kernarg_i16_to_i8:
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; SI: s_load_dword s
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_kernarg_i16_to_i8(i8 addrspace(1)* %out, i16 %arg) nounwind {
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%trunc = trunc i16 %arg to i8
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store i8 %trunc, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_buffer_load_i16_to_i8:
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; SI: buffer_load_ubyte v
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_buffer_load_i16_to_i8(i8 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i16, i16 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
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%load = load i16, i16 addrspace(1)* %gep.in
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%trunc = trunc i16 %load to i8
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store i8 %trunc, i8 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}srl_kernarg_i64_to_i8:
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; SI: s_load_dword s
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; SI: buffer_store_byte v
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define amdgpu_kernel void @srl_kernarg_i64_to_i8(i8 addrspace(1)* %out, [8 x i32], i64 %arg) nounwind {
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%srl = lshr i64 %arg, 32
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%trunc = trunc i64 %srl to i8
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store i8 %trunc, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}srl_buffer_load_i64_to_i8:
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; SI: buffer_load_dword v
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; SI: buffer_store_byte v
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define amdgpu_kernel void @srl_buffer_load_i64_to_i8(i8 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
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%load = load i64, i64 addrspace(1)* %gep.in
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%srl = lshr i64 %load, 32
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%trunc = trunc i64 %srl to i8
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store i8 %trunc, i8 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_kernarg_i64_to_i8:
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; SI: s_load_dword s
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_kernarg_i64_to_i8(i8 addrspace(1)* %out, [8 x i32], i64 %arg) nounwind {
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%trunc = trunc i64 %arg to i8
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store i8 %trunc, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}truncate_buffer_load_i64_to_i8:
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; SI: buffer_load_dword v
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; SI: buffer_store_byte v
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define amdgpu_kernel void @truncate_buffer_load_i64_to_i8(i8 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
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%load = load i64, i64 addrspace(1)* %gep.in
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%trunc = trunc i64 %load to i8
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store i8 %trunc, i8 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}smrd_mask_i32_to_i16
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; SI: s_load_dword [[LOAD:s[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0x0
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; SI: s_waitcnt lgkmcnt(0)
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; SI: s_and_b32 s{{[0-9]+}}, [[LOAD]], 0xffff
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define amdgpu_kernel void @smrd_mask_i32_to_i16(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
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entry:
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%val = load i32, i32 addrspace(4)* %in
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%mask = and i32 %val, 65535
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store i32 %mask, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}extract_hi_i64_bitcast_v2i32:
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; SI: buffer_load_dword v
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; SI: buffer_store_dword v
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define amdgpu_kernel void @extract_hi_i64_bitcast_v2i32(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
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%ld = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%bc = bitcast <2 x i32> %ld to i64
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%hi = lshr i64 %bc, 32
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%trunc = trunc i64 %hi to i32
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store i32 %trunc, i32 addrspace(1)* %out
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ret void
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}
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