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dfc42ff390
This covers tests starting with m-r. Differential Revision: https://reviews.llvm.org/D94181
182 lines
7.4 KiB
LLVM
182 lines
7.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-flat-for-global -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; GCN-LABEL: {{^}}s_pack_v2i16:
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; GFX9: s_load_dword [[VAL0:s[0-9]+]]
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; GFX9: s_load_dword [[VAL1:s[0-9]+]]
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; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @s_pack_v2i16(i32 addrspace(4)* %in0, i32 addrspace(4)* %in1) #0 {
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%val0 = load volatile i32, i32 addrspace(4)* %in0
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%val1 = load volatile i32, i32 addrspace(4)* %in1
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%lo = trunc i32 %val0 to i16
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%hi = trunc i32 %val1 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}s_pack_v2i16_imm_lo:
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; GFX9: s_load_dword [[VAL1:s[0-9]+]]
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; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1c8, [[VAL1]]
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @s_pack_v2i16_imm_lo(i32 addrspace(4)* %in1) #0 {
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%val1 = load i32, i32 addrspace(4)* %in1
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%hi = trunc i32 %val1 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 456, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}s_pack_v2i16_imm_hi:
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; GFX9: s_load_dword [[VAL0:s[0-9]+]]
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; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1c8
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @s_pack_v2i16_imm_hi(i32 addrspace(4)* %in0) #0 {
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%val0 = load i32, i32 addrspace(4)* %in0
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%lo = trunc i32 %val0 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 456, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}v_pack_v2i16:
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; GFX9: global_load_dword [[VAL0:v[0-9]+]]
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; GFX9: global_load_dword [[VAL1:v[0-9]+]]
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; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
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; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[MASKED]]
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @v_pack_v2i16(i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
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%in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
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%val0 = load volatile i32, i32 addrspace(1)* %in0.gep
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%val1 = load volatile i32, i32 addrspace(1)* %in1.gep
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%lo = trunc i32 %val0 to i16
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%hi = trunc i32 %val1 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}v_pack_v2i16_user:
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; GFX9: global_load_dword [[VAL0:v[0-9]+]]
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; GFX9: global_load_dword [[VAL1:v[0-9]+]]
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; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
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; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[MASKED]]
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 9, [[PACKED]]
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define amdgpu_kernel void @v_pack_v2i16_user(i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
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%in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
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%val0 = load volatile i32, i32 addrspace(1)* %in0.gep
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%val1 = load volatile i32, i32 addrspace(1)* %in1.gep
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%lo = trunc i32 %val0 to i16
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%hi = trunc i32 %val1 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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%foo = add i32 %vec.i32, 9
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store volatile i32 %foo, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_pack_v2i16_imm_lo:
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; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]]
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; GFX9-DENORM-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7b{{$}}
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; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b{{$}}
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; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[K]]
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @v_pack_v2i16_imm_lo(i32 addrspace(1)* %in1) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
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%val1 = load volatile i32, i32 addrspace(1)* %in1.gep
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%hi = trunc i32 %val1 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 123, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}v_pack_v2i16_inline_imm_lo:
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; GFX9: global_load_dword [[VAL1:v[0-9]+]]
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; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, 64
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @v_pack_v2i16_inline_imm_lo(i32 addrspace(1)* %in1) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in1.gep = getelementptr inbounds i32, i32 addrspace(1)* %in1, i64 %tid.ext
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%val1 = load volatile i32, i32 addrspace(1)* %in1.gep
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%hi = trunc i32 %val1 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 64, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}v_pack_v2i16_imm_hi:
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; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]]
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; GFX9-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7b{{$}}
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; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[K]], 16, [[VAL0]]
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @v_pack_v2i16_imm_hi(i32 addrspace(1)* %in0) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
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%val0 = load volatile i32, i32 addrspace(1)* %in0.gep
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%lo = trunc i32 %val0 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 123, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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; GCN-LABEL: {{^}}v_pack_v2i16_inline_imm_hi:
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; GFX9: global_load_dword [[VAL:v[0-9]+]]
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; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], 7, 16, [[VAL]]
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; GFX9: ; use [[PACKED]]
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define amdgpu_kernel void @v_pack_v2i16_inline_imm_hi(i32 addrspace(1)* %in0) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds i32, i32 addrspace(1)* %in0, i64 %tid.ext
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%val0 = load volatile i32, i32 addrspace(1)* %in0.gep
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%lo = trunc i32 %val0 to i16
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%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
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%vec.1 = insertelement <2 x i16> %vec.0, i16 7, i32 1
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%vec.i32 = bitcast <2 x i16> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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