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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
22 lines
1.0 KiB
YAML
22 lines
1.0 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx908 %s -run-pass=post-RA-sched -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: test
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# GCN: V_MFMA_F32_32X32X1F32
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# GCN: S_BARRIER
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# GCN: V_ACCVGPR_READ_B32
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# GCN: BUFFER_STORE_DWORD_OFFEN
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---
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name: test
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body: |
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bb.0.entry:
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$sgpr6 = S_MOV_B32 $sgpr5
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$sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr0_sgpr1_sgpr2_sgpr3
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$sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
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S_BARRIER
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$agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X1F32_e64 undef $vgpr0, undef $vgpr0, 0, 0, 0, 2, implicit $mode, implicit $exec
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$vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec
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BUFFER_STORE_DWORD_OFFEN killed $vgpr0, undef $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr6, 0, 0, 0, 0, implicit $exec
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...
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