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ba5c703719
Use the KnownBits icmp comparisons to determine when a ISD::UMIN/UMAX op is unnecessary should either op be known to be ULT/ULE or UGT/UGE than the other. Differential Revision: https://reviews.llvm.org/D94532
36 lines
1.3 KiB
LLVM
36 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=r600 -mcpu=cypress -start-after safe-stack | FileCheck %s
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; Don't crash
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define amdgpu_kernel void @test(i64 addrspace(1)* %out) {
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; CHECK-LABEL: test:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: ALU 4, @6, KC0[CB0:0-32], KC1[]
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; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 0
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; CHECK-NEXT: ALU 3, @11, KC0[], KC1[]
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; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: PAD
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; CHECK-NEXT: ALU clause starting at 6:
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; CHECK-NEXT: MOV T0.X, literal.x,
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; CHECK-NEXT: MOV T0.Y, 0.0,
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; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CHECK-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; CHECK-NEXT: MOV * T0.W, KC0[2].Y,
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; CHECK-NEXT: ALU clause starting at 11:
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; CHECK-NEXT: MOV T0.X, literal.x,
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; CHECK-NEXT: MOV T0.Y, 0.0,
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; CHECK-NEXT: LSHR * T1.X, T0.W, literal.y,
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; CHECK-NEXT: 4(5.605194e-45), 2(2.802597e-45)
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bb:
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store i64 2, i64 addrspace(1)* %out
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%tmp = load i64, i64 addrspace(1)* %out
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br label %jump
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jump: ; preds = %bb
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%tmp1 = icmp ugt i64 %tmp, 4
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%umax = select i1 %tmp1, i64 %tmp, i64 4
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store i64 %umax, i64 addrspace(1)* %out
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ret void
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}
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