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d1f23a1772
Support for XNACK and SRAMECC is not static on some GPUs. We must be able to differentiate between different scenarios for these dynamic subtarget features. The possible settings are: - Unsupported: The GPU has no support for XNACK/SRAMECC. - Any: Preference is unspecified. Use conservative settings that can run anywhere. - Off: Request support for XNACK/SRAMECC Off - On: Request support for XNACK/SRAMECC On GCNSubtarget will track the four options based on the following criteria. If the subtarget does not support XNACK/SRAMECC we say the setting is "Unsupported". If no subtarget features for XNACK/SRAMECC are requested we must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the feature string when initializing the subtarget, the settings are "On/Off". The defaults are updated to be conservatively correct, meaning if no setting for XNACK or SRAMECC is explicitly requested, defaults will be used which generate code that can be run anywhere. This corresponds to the "Any" setting. Differential Revision: https://reviews.llvm.org/D85882
43 lines
1.7 KiB
LLVM
43 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i32 @llvm.amdgcn.sffbh.i32(i32) nounwind readnone speculatable
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define amdgpu_kernel void @select_constant_cttz(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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; GCN-LABEL: select_constant_cttz:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dword s2, s[2:3], 0x0
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_lshr_b32 s0, 1, s2
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; GCN-NEXT: s_ff1_i32_b32 s0, s0
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, 0
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; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[2:3]
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; GCN-NEXT: v_ffbh_i32_e32 v1, v0
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; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
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; GCN-NEXT: v_sub_i32_e32 v0, vcc, 31, v1
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[0:1]
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; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%v = load i32, i32 addrspace(1)* %arrayidx, align 4
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%sr = lshr i32 1, %v
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%cmp = icmp ne i32 %v, 0
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%cttz = call i32 @llvm.cttz.i32(i32 %sr, i1 true), !range !0
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%sel = select i1 %cmp, i32 -1, i32 %cttz
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%ffbh = call i32 @llvm.amdgcn.sffbh.i32(i32 %sel)
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%sub = sub i32 31, %ffbh
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%cmp2 = icmp eq i32 %sel, 0
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%or = or i1 %cmp, %cmp2
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%sel2 = select i1 %or, i32 -1, i32 %sub
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store i32 %sel2, i32 addrspace(1)* %out
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ret void
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}
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!0 = !{i32 0, i32 33}
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